Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an are enclosed by the oxide material formed in the opening.

Abstract: A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.

Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate; a channel region of a first type conductivity, defined in the fin active region and having a first carrier concentration; and an anti-punch through (APT) feature of the first type conductivity, wherein the APT feature is formed in the semiconductor substrate, is directly underlying the channel region, and has a second carrier concentration greater than the first carrier concentration.

Abstract: Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition.

Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.

Abstract: The semiconductor structure includes a plurality of first insulators in a substrate, a common insulating layer surrounding the sidewall and the bottom of said first insulators in said substrate, and suspended portions of said substrate on said common insulating layer.

Abstract: Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a first resist-mask on top of a first portion of the hard-mask layer and applying the first resist-mask in forming a first type of wells in a first region of the substrate; forming a second resist-mask on top of a second portion of the hard-mask layer and applying the second resist-mask in forming a second type of wells in a second region of the substrate; applying the first and second resist-masks in transforming the hard-mask layer into a hard-mask, the hard-mask having openings aligned to areas overlapped by the first and second regions of the substrate; etching at least the areas of the substrate in creating deep trenches that separate the first and second types of wells; and filling the deep trenches with insulating materials.

Abstract: A method of forming an isolated device region. The isolated device region may include forming a first trench in a second dielectric and a first dielectric, the second dielectric is on the first dielectric, the first dielectric is on a substrate; growing a semiconductor channel in the first trench, a top portion of the semiconductor channel is a device region and a bottom portion of the semiconductor channel is a defect region; removing the second dielectric layer exposing a portion of device region; recessing the first dielectric layer exposing a trench region of the semiconductor channel, the trench region is a region between the device region and the defect region; removing the trench region of the semiconductor channel electrically isolating the device region from the defect region; and forming a barrier layer between the isolated device region and the defect region.

Abstract: A backside contact structure is created using the following sequence of steps: etching a deep trench from the front surface of the semiconductor wafer to the buried layer to be contacted; depositing an isolation layer into the trench which covers the surfaces of the trench; performing an ion beam anisotropic etch in order to selectively etch the isolation layer at the bottom of the trench; filling the trench with a conductive material in order to create an electrical connection to the backside layer. The process can either be performed at a front-end stage of wafer processing following the formation of shallow trench isolation structures, or at a back-end stage after device transistors are formed. The backside contact structure so fabricated is used to electrically isolate circuit structures constructed on the wafer's upper surface, so that the various components of an integrated circuit can operate at different reference voltages.

Abstract: An etch mask is formed on a substrate. The substrate is positioned in an enclosure configured to shield an interior of the enclosure from electromagnetic fields exterior to the enclosure; and the substrate is etched in the enclosure, including removing a portion of the substrate to form a structure having at least a portion that is isolated and/or suspended over the substrate.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: A semiconductor device includes: a first well and a second well formed in a substrate and having a different impurity doping concentration; a first isolation layer and a second isolation layer formed in the first well and the second well, respectively, and having a different depth; and a third isolation layer formed in a boundary region in which the first well and the second well are in contact with each other, and having a combination type of the first isolation layer and the second isolation layer.

Abstract: Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

Abstract: In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.

Abstract: Methods for making a semiconductor device are disclosed. The method includes forming a plurality of gate stacks on a substrate, forming an etch buffer layer on the substrate, forming a dielectric material layer on the etch buffer layer, forming a hard mask layer on the substrate, wherein the hard mask layer includes one opening, and etching the dielectric material layer to form a plurality of trenches using the hard mask layer and the etch buffer layer as an etch mask.

Abstract: A phase change memory cell includes a first electrode having a cylindrical portion. A dielectric material having a cylindrical portion is longitudinally over the cylindrical portion of the first electrode. Heater material is radially inward of and electrically coupled to the cylindrical portion of the first electrode. Phase change material is over the heater material and a second electrode is electrically coupled to the phase change material. Other embodiments are disclosed, including methods of forming memory cells which include first and second electrodes having phase change material and heater material in electrical series there-between.

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.

Abstract: According to example embodiments, there is provided a semiconductor device including a substrate and an isolation layer structure. The substrate includes an active region having an upper active pattern and a lower active pattern on the upper active pattern. The active region has a first aspect ratio larger than about 13:1 and a second aspect ratio smaller than about 13:1. The first aspect ratio is defined as a ratio of a sum of heights of the upper active pattern and the lower active pattern with respect to a width of the upper active pattern. The second aspect ratio is defined as a ratio of the sum of the heights of the upper active pattern and the lower active pattern with respect to a width of the lower active pattern. The isolation layer structure is adjacent to the active region.

Abstract: A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

Abstract: A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

Abstract: A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region.

Abstract: In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.

Abstract: Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. A preferred embodiment includes forming at least one trench in a workpiece, and forming a thin nitride liner over sidewalls and a bottom surface of the at least one trench and over a top surface of the workpiece using atomic layer deposition (ALD). An insulating material is deposited over the top surface of the workpiece, filling the at least one trench. At least a portion of the insulating material is removed from over the top surface of the workpiece. After removing the at least a portion of insulating material from over the top surface of the workpiece, the thin nitride liner in the at least one trench is at least coplanar with the top surface of the workpiece. The thin nitride liner and the insulating material form an isolation region of the semiconductor device.

Abstract: Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract: Methods of forming a semiconductor trench and forming dual trenches and a structure for isolating devices are provided. The structure for isolating devices is disposed in a substrate having a periphery area and an array area. The structure for isolating devices includes a first isolation structure and a second isolation structure. The first isolation structure has a profile with at least three steps and is disposed in the substrate in the periphery area. The second isolation structure has a profile with at least two steps and is disposed in the substrate in the array area.

Abstract: A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

Abstract: Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

Abstract: A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.

Abstract: A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.

Abstract: Methods of forming a semiconductor trench and forming dual trenches and a structure for isolating devices are provided. The structure for isolating devices is disposed in a substrate having a periphery area and an array area. The structure for isolating devices includes a first isolation structure and a second isolation structure. The first isolation structure has a profile with at least three steps and is disposed in the substrate in the periphery area. The second isolation structure has a profile with at least two steps and is disposed in the substrate in the array area.

Abstract: In a method of forming an asymmetric recess, an asymmetric recessed gate structure filling the asymmetric recess, a method of forming the asymmetric recessed gate structure, a semiconductor device having the asymmetric recessed gate structure and a method of manufacturing the semiconductor device, a semiconductor substrate is etched to form a first sub-recess having a first central axis. A second sub-recess is formed under the first sub-recess. The second sub-recess is in communication with the first sub-recess. The second sub-recess has a second central axis substantially parallel with the first central axis. The second central axis is spaced apart from the first central axis.

Abstract: A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

Abstract: An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers.

Abstract: Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a surface of the substrate and having a first pair of opposing sidewalls that are each substantially perpendicular to the surface of the substrate. A second isolation trench portion includes a second pair of sidewalls within the substrate that are each angled obliquely with respect to the surface of the substrate, where the second isolation trench portion has a separation between the second pair of sidewalls that decreases as a distance from the first isolation trench portion increases. A third isolation trench portion includes a third pair of sidewalls within the substrate that are each substantially perpendicular to the surface of the substrate.

Abstract: A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation structure, and a protruding part overlying the boundary of the active region and the isolation structure.

Abstract: A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable Idsat characteristics may then be formed.

Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

Abstract: A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first photoresist pattern as a mask. Removing the first photoresist pattern. Filling the trench with a trench oxide layer. Planarizing the trench oxide layer. Forming an etch stop layer on and/or over the trench oxide layer. Forming a second photoresist pattern on and/or over the etch stop layer. Etching the etch stop layer and the trench oxide layer using the second photoresist pattern as an etch mask. Removing the second photoresist pattern and the etch stop layer.

Abstract: A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature.

Abstract: A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend.

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract: A process for fabrication of a semiconductor device that includes forming a first trench in a semiconductor body, forming spaced spacers in the first trench, and forming a narrower second trench at the bottom of the first trench using the spacers as a mask.

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.