Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC structure according to embodiments of the present invention may include a through-semiconductor via (TSV) embedded within a substrate, the TSV having an axial end; and a metal cap contacting the axial end of the TSV, wherein the metal cap has a greater electrical resistivity than the TSV.

Abstract: A SRAM cell and a forming method thereof are provided. The SRAM cell includes: a pull-up transistor, a pull-down transistor, a pass gate transistor, a tensile stress film which covers the pull-up transistor and the pull-down transistor, and an interlayer dielectric isolating layer which covers the tensile stress film and the pass gate transistor. The method includes: providing a semiconductor substrate; forming a pull-up transistor, a pull-down transistor and a pass gate transistor on the semiconductor substrate; forming a tensile stress film covering the pull-up and pull-down transistors; and forming an interlayer dielectric isolating layer covering the tensile stress film and the pass gate transistor. Write margin of the SRAM cell may be increased and an area of the SRAM cell may be reduced.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.

Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

Abstract: A semiconductor memory device includes a block decoder configured to output block selection signals for selecting memory blocks in response to a row address signal, a first memory block including a first drain select line, a first source select line, and a first word line group including a plurality of first word lines disposed between the first drain select line and the first source select line, the first memory block disposed between the block decoder and a first switching group, the first switching group configured to transmit first operating voltages to the first memory block in response to a first block selection signal among the block selection signals, and a first block word line configured to transmit the first block selection signal to the first switching group and disposed over the first memory block to avoid overlapping with the first word line group.

Abstract: A semiconductor device is manufactured by forming a first dielectric film on a substrate, forming an aperture in the first dielectric film, mounting a semiconductor chip in the aperture, forming a second dielectric film on the first dielectric film and the semiconductor chip, and forming an interconnection wiring structure on the second dielectric film. The second dielectric film secures the semiconductor chip without the need to etch the substrate or use an adhesive die attachment film.

Abstract: Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.

Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

Abstract: By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract: A method for producing an electrical feedthrough in a substrate includes: forming a first printed conductor on a first side of a substrate which electrically connects a first contact area of the substrate on the first side; forming a second printed conductor on a second side of a substrate which electrically connects a second contact area of the substrate on the second side; forming an annular trench in the substrate, a substrate punch being formed which extends from the first contact area to the second contact area; and selectively depositing an electrically conductive layer on an inner surface of the annular trench, the substrate punch being coated with an electrically conductive layer and remaining electrically insulated from the surrounding substrate due to the annular trench.

Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.

Abstract: An approach for providing bit cells with triple patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process of a metal layer, a first structure that is a first one of a word line structure, a ground line structure, a power line structure, and a bit line structure; providing, via a second patterning process of the metal layer, a second structure that is different from the first structure and that is a second one of the word line structure, the ground line structure, the power line structure, and the bit line structure; and providing, via a third patterning process of the metal layer, a third structure that is different from the first structure and the second structure, and that is a third one of the word line structure, the ground line structure line, the power line structure, and the bit line structure.

Abstract: A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first and second passivation layers around the copper bond pad; etching the second passivation layer over the copper bond pad; and cleaning the first passivation layer over the copper bond pad. At least a portion of the first passivation layer remains over the copper bond pad after the etching the second passivation layer. A thickness of the first passivation layer over the copper bond pad is selected to protect the copper bond pad from oxidation and to allow wire bonding to the copper bond pad through the first passivation layer.

Abstract: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.

Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.

Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

Abstract: A method for filling a metal is disclosed. First, a substrate is provided. The substrate includes a metal material layer, a dielectric layer covering the metal material layer and a hard mask layer covering the dielectric layer. The hard mask layer has at least one opening to expose the underlying dielectric layer. Second, a dry etching step is performed to etch the dielectric layer through the opening to remove part of the dielectric layer to expose the metal material layer and to form a recess and leave some residues in the recess. Then a cleaning step is performed to remove the residues and to selectively remove part of the hard mask to substantially enlarge the opening. Later, a metal fills the recess through the enlarged opening.

Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.

Abstract: A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver.

Abstract: A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.

Abstract: A semiconductor device includes a compound semiconductor layer provided over a substrate, a plurality of source electrodes and a plurality of drain electrodes provided over the compound semiconductor layer, a plurality of first vias each of which is configured to pass through the compound semiconductor layer and be coupled to a corresponding one of the plurality of source electrodes, a plurality of second vias each of which is configured to pass through the compound semiconductor layer and be coupled to a corresponding one of the plurality of drain electrodes, a common source wiring line configured to be coupled to the plurality of first vias and be buried in the substrate, and a common drain wiring line configured to be coupled to the plurality of second vias and be buried in the substrate.

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate, except on the first wire; forming a surface treatment film on the material layer; and forming a second wire on the first wire. The surface treatment film has physical properties opposite to the first wire. A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate and the first wire; removing a portion of the material layer from the first wire; forming a surface treatment film on the material layer and the first wire; removing a portion of the surface treatment film from the first wire; and forming a second wire on the first wire. A thickness of the material layer on the substrate is greater than a thickness of the first wire on the substrate.

Abstract: A method of depositing a film with a target conformality on a patterned substrate, includes: depositing a first film on a convex pattern and a bottom surface; and depositing a second film on the first film, thereby forming an integrated film having a target conformality, wherein one of the first and second films is a conformal film which is non-flowable when being deposited and has a conformality of about 80% to about 100%, and the other of the first and second films is a flowable film which is flowable when being deposited.

Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.

Abstract: An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.

Abstract: A method of inspecting a semiconductor substrate having a back surface and including at least one piece of metal embedded in the substrate comprises directing measuring light towards the back surface of the substrate and detecting a portion of the measuring light received back from the substrate. The method also includes determining a distance between the piece of metal and the back surface based upon the detected measuring light received back from the substrate.

Abstract: A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) device on a structure that includes a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device including a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis.

Abstract: A nonvolatile memory apparatus includes a a memory cell array, a page buffer unit connected to bit lines of the memory cell array through a high voltage switching unit, a first interconnection configured to connect a high voltage switch of the high voltage switching unit, connected to an even bit line, to the page buffer unit, and formed at a first layer, and a second interconnection configured to connect a high voltage switch of the high voltage switching unit, connected to an odd bit line, to the page buffer unit, and formed at a second layer different from the first layer.

Abstract: A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions.

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract: The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.

Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.

Abstract: Patterning-induced damage of sensitive low-k dielectric materials in semiconductors devices may be restored to a certain degree on the basis of a surface treatment that is performed prior to exposing the device to ambient atmosphere. To this end, the dangling silicon bonds of the silicon oxide-based low-k dielectric material may be saturated in a confined process environment, thereby providing superior surface conditions for the subsequent application of an appropriate repair chemistry.

Abstract: A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.

Abstract: A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.

Abstract: An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.

Abstract: A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

Abstract: An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: A method for the fabrication of a semiconductor chip, comprises forming one or more semiconductor devices on a substrate; forming a passivation layer on the substrate; forming a plurality of bond pads on the passivation layer; and forming a plurality of under-bump metallurgy (UBM) layers on respective ones of the plurality of bond pads, wherein at least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center of the chip to the periphery thereof.

Abstract: Selective deposition of metal over dielectric layers in a manner that minimizes of eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured as allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer.

Abstract: A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a first contact pad at a first main side of the first substrate; providing a second substrate with a second main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the second main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the second main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area