Abstract: An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric layer. The dual damascene structure includes a second conductive line and a via between and adjoining the first and the second conductive lines, wherein the second conductive line comprises a first portion directly over and adjoining the via, and a second portion having no underlying and adjoining vias. The second portion has a second width less than a first width of the first portion.

Abstract: Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

Abstract: One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening.

Abstract: A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode.

Abstract: Methods of manufacturing a semiconductor device include forming a stopping layer pattern in a first region of a substrate. A first mold structure is formed in a second region of the substrate that is adjacent the first region. The first mold structure includes first sacrificial patterns and first interlayer patterns stacked alternately. A second mold structure is formed on the first mold structure and the stopping layer pattern. The second mold structure includes second sacrificial patterns and second interlayer patterns stacked alternately. The second mold structure partially covers the stopping layer pattern. A channel pattern is formed and passes through the first mold structure and the second mold structure.

Abstract: A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.

Abstract: Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a second insulation layer on the first insulation layer, the second insulation layer including a metal head pattern, a thin film resistor pattern on the metal head pattern, a third insulation layer on the thin film resistor pattern, an upper metal line on the third insulation layer, a first via passing through the first, second, and third insulation layers to connect the lower metal line to the upper metal line, and a second via passing through the third insulation layer and the thin film resistor pattern to connect the metal head pattern to the upper metal line.

Abstract: An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher elastic modulus than Cu; a second insulating film on the first insulating film; and a via plug composed of Cu and arranged in the second insulating film, the via plug being in contact with the metal film.

Abstract: According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

Abstract: A power layout of an integrated circuit includes at least one power grid cell. Each power gird cell includes at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The at least one first power layer has conductive lines in at least two different directions. The at least one second power layer has conductive lines in at least two different directions.

Abstract: A method for forming interconnects in a substrate, the substrate comprising a semiconductor layer on an oxide layer forming a silicon-on-oxide substrate, the method comprising forming a plurality of holes into the substrate to the semiconductor layer, and metalizing the plurality of holes to form the interconnects.

Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate including a first surface and a second surface opposite to the first surface, and a through-via penetrating the semiconductor substrate. The through-via has a stacked structure of a first conductive film formed in a portion of the semiconductor substrate closer to the first surface, and a second conductive film formed in a portion of the semiconductor substrate closer to the second surface. An insulating layer is buried inside the semiconductor substrate. The first conductive film is electrically connected to the second conductive film in the insulating layer.

Abstract: A method of fabricating a substrate having a plurality of conductive through holes is disclosed. Release films are formed on opposite sides of a substrate, and a plurality of through holes penetrating the release films and the substrate are formed. A first metal layer is formed on the release films and the sidewall of each of the through holes prior to removing the release films and the first metal layer thereon. A second metal layer is formed on the first metal layer on the sidewalls of the through holes by electroless plating. Compared to the prior art, the method is simpler and cheaper to carry out while the conductive through holes and a surface circuit layer thereof are fabricated separately, thereby avoiding disadvantage of forming a circuit layer on the surface of the substrate too thick.

Abstract: The application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises: a semiconductor substrate comprising a first surface and a second surface opposite to each other; and a silicon via formed through the semiconductor substrate, wherein the silicon via comprises a first via formed through the first surface; and a second via formed through the second surface and electrically connected with the first via, wherein the first and second vias are formed individually. Embodiments of the invention are applicable to the manufacture of a 3D integrated circuit.

Abstract: A chip includes a first circuit, a second circuit, a first interconnect, and a least one protection circuit. The first circuit has a first node, a first operational voltage node, and a first reference voltage node. The second circuit has a second node, a second operational voltage node, and a second reference voltage node. The first interconnect is configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit. The at least one protection circuit is located at one or various locations of the chip.

Abstract: An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.

Abstract: In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

Abstract: A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film.

Abstract: In a method for fabricating a semiconductor device, a semiconductor device is provided including an interlayer dielectric film and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric film through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric film and the first and second hard mask patterns to fill the first trench. First and second hard mask trimming patterns are formed by trimming sidewalls of the first and second hard mask patterns and removing the filler material to expose the first trench. A damascene wire is formed by filling the first trench with a conductive material.

Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

Abstract: A component including a via for electrical connection between a first and a second plane of a substrate is provided. The substrate has a borehole having an inner wall that is coated with a conductive layer made of an electrically conductive material, an intermediate layer being disposed between the inner wall and the conductive layer. The intermediate layer includes electrically insulating SiC.

Abstract: An integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates where the transistor gate contact length is less than about 3 times the width. A method for forming an integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates where the transistor gate contact length is less than about 3 times the width.

Abstract: A method for forming an integrated circuit system includes providing an integrated circuit device; and forming an integrated contact over the integrated circuit device including: providing a via over the integrated circuit device; forming a selective metal in the via; forming at least one nanotube over the selective metal; and forming a cap over the nanotubes.

Abstract: An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns.

Abstract: The present disclosure relates to the field of microelectronic substrate fabrication and, more particularly, to alignment inspection for vias formed in the microelectronic substrates. The alignment inspection may be achieved by determining the relative positions of fluorescing and non-fluorescing elements in a microelectronic substrate.

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.

Abstract: A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance.

Abstract: A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.

Abstract: When forming contact levels of sophisticated semiconductor devices, a superior bottom to top fill behavior may be accomplished by applying an activation material selectively in the lower part of the contact openings and using a selective deposition technique. Consequently, deposition-related irregularities, such as voids, may be efficiently suppressed even for high aspect ratio contact openings.

Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Abstract: Provided is a semiconductor device manufacturing method enabling miniaturization by forming a hole in a vertical shape, capable of reducing the number of processes as compared to conventional methods, and capable of increasing productivity. The semiconductor device manufacturing method includes: forming a hole in a substrate; forming a polyimide film within the hole; isotropically etching the substrate without using a mask covering a sidewall portion of the polyimide film within the hole and removing at least a part of a bottom portion of the polyimide film within the hole while the sidewall portion of the polyimide film remains within the hole; and filling the hole with a conductive metal.

Abstract: Provided is a plasma reactor having a dual inductively coupled plasma source that includes a plasma reactor body having a substrate processing area and a dielectric window which comes in contact with the substrate processing area; and a plasma source including a first antenna for providing first induced electromotive force for generating plasma onto a central area of the substrate processing area through the dielectric window and a second antenna for providing second induced electromotive force for generating the plasma onto an outer area of the substrate processing area, wherein a TSV is formed at a target substrate within the substrate processing area by repeatedly performing a deposition process and an etch process using the plasma generated through the dual inductively coupled plasma source.

Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.

Abstract: Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this manner, the patterning process for forming the via openings may be controlled in a highly reliable manner, while, on the other hand, the resulting overall dielectric constant of the metallization system may be reduced, thereby also significantly reducing the parasitic capacitance between stacked metal lines.

Abstract: A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked.

Abstract: A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

Abstract: Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.

Abstract: Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures.

Abstract: An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.

Abstract: An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.

Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A multi-layered structure is prepared over a semiconductor substrate. The multi-layered structure may include, but is not limited to, first and second patterns of a first insulating film, a second insulating film covering the first pattern of the first insulating film, and a first conductive film covering the second pattern of the first insulating film. The second insulating film and the first conductive film are polished under conditions that the first and second insulating films are greater in polishing rate than the first conductive film, to expose the first and second patterns of the first insulating film.

Abstract: Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection.

Abstract: One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.

Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.

Abstract: A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material.