Substrate Being Semiconductor, Using Silicon Technology (epo) Patents (Class 257/E21.607)
  • Patent number: 7459704
    Abstract: Ion sources and methods for generating molecular ions in a cold operating mode and for generating atomic ions in a hot operating mode are provided. In some embodiments, first and second electron sources are located at opposite ends of an arc chamber. The first electron source is energized in the cold operating mode, and the second electron source is energized in the hot operating mode. In other embodiments, electrons are directed through a hole in a cathode in the cold operating mode and are directed at the cathode in the hot operating mode. In further embodiments, an ion beam generator includes a molecular ion source, an atomic ion source and a switching element to select the output of one of the ion sources.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: December 2, 2008
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Joseph C. Olson, Anthony Renau, Donna L. Smatlak, Kurt Deckerlucke, Paul Murphy, Alexander S. Perel, Russell J. Low, Peter Kurunczi
  • Patent number: 7414305
    Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: August 19, 2008
    Assignee: Spansion LLC
    Inventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
  • Patent number: 7208392
    Abstract: A method of creating an electrically conducting bonding between a face of a first semiconductor element and a face of a second semiconductor element using heat treatment. The method applies the faces one against the other with the placing between them of at least one layer of a material configured to provide, after heat treatment, an electrically conducting bonding between the two faces. The deposited layers are chosen so that the heat treatment does not induce any reaction product between said material and the semi-conductor elements. Then, a heat treatment is carried out.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: April 24, 2007
    Assignee: Soitec
    Inventors: Claude Jaussaud, Eric Jalaguier, Roland Madar