Abstract: A semiconductor device includes an active region and a dummy active region formed in a semiconductor substrate to have a distance from each other, an isolation region formed between the active region and the dummy active region and has a top surface lower than top surfaces of the active region and the dummy active region, a gate insulating film formed on the active region and a fully silicided gate electrode formed on the isolation region, the gate insulating film and the dummy active region through full silicidation of a silicon gate material film with metallic material.

Abstract: A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the metal film, the metal nitride film and the metal silicide film to pattern them into the shape of a gate such that the portion of the meal silicide film that forms part of a gate electrode of a P-type MOSFET and the portion of the meal silicide film that forms part of a gate electrode of an N-type MOSFET are separated from each other; introducing P-type and N-type impurities into the respective regions of the non-doped polysilicon film where the P-type and N-type MOSFETs are formed; performing thermal treatment to diffuse the impurities; and patterning the polysilicon film with the impurities introduced into the shape of the gate.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region of the semiconductor substrate; a fully silicided first gate line formed on the active region; a fully silicided second gate line formed on the isolation region; a first sidewall formed on a side of the first gate line; a second sidewall formed on a side of the second gate line. The length between the top and bottom surfaces of the first sidewall is different from that between the top and bottom surfaces of the second sidewall.

Abstract: A method for forming a memory device is provided. A first layer is formed over a substrate. A second layer is formed over the first layer. A mask is formed over the second layer. Spacers are formed adjacent opposite sides of the mask. The second layer is etched to form at least one memory cell stack. The memory device is cleaned to remove the mask. A silicide region is formed within the second layer in the at least one memory cell stack, where the silicide region in each memory cell stack is bounded by the spacers.

Abstract: A semiconductor device includes a MISFET, the MISFET having a shallow trench insulator (STI) formed in a surface layer of a semiconductor substrate to define a device forming region, a gate electrode formed above the device forming region via a gate insulating film, impurity diffusion layers composing a source and a drain formed in the surface layer of the device forming region using SiGe so as to sandwich the gate electrode, and a first metal silicide formed on the surfaces of the impurity diffusion layers. The surface height of the STI is substantially the same as the height of the first metal silicide.

Abstract: An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavity (6), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate (7) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer (5) by Coulomb interactive force between the electrons (or positive holes 8) accumulated in the floating gate layer (5) and external electric field, and by reading the channel current change based on the state of the floating gate layer (5).

Abstract: A silicided gate for CMOS transistors and a method of manufacture is provided. A gate electrode is formed on a substrate. A first dielectric layer is formed over the gate electrode and the substrate, and a second dielectric layer is formed over the first dielectric layer. The second dielectric layer is etched to form spacers adjacent the gate electrode. A treatment is performed on the first dielectric layer over the gate electrode, wherein the treatment increases the effective etch rate of the first dielectric layer as compared to untreated portions of the first dielectric layer. An etching procedure is then performed to expose the surface of the gate electrode, the etching procedure recessing the liner along sidewalls of the gate electrode. Thereafter, a silicide procedure is performed to silicide at least a portion of the gate electrode.

Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Abstract: Raised Si/SiGe source and drain regions include epitaxially grown silicon on SiGe sidewalls. The epi silicon prevents adverse effects of Ge during silicidation, including Ge out diffusion and silicide line breakage. The Si also increases the active area.

Abstract: A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the metal film, the metal nitride film and the metal silicide film to pattern them into the shape of a gate such that the portion of the meal silicide film that forms part of a gate electrode of a P-type MOSFET and the portion of the meal silicide film that forms part of a gate electrode of an N-type MOSFET are separated from each other; introducing P-type and N-type impurities into the respective regions of the non-doped polysilicon film where the P-type and N-type MOSFETs are formed; performing thermal treatment to diffuse the impurities; and patterning the polysilicon film with the impurities introduced into the shape of the gate.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

Abstract: A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polysilicon layer not masked by the resist mask, thereby forming a gate electrode; etching a thickness of the gate dielectric layer not covered by the gate electrode; stripping the resist mask; forming a salicide block resist mask covering the gate electrode and a portions of the remaining gate dielectric layer; etching away the remaining gate dielectric layer not covered by the salicide block resist mask, thereby exposing the substrate and forming a salicide block lug portions on two opposite sides of the gate electrode; and making a metal layer react with the substrate, thereby forming a salicide layer that is kept a distance “d” away from the gate electrode.