Isolation Region Manufacturing Related Aspects, E.g., To Avoid Interaction Of Isolation Region With Adjacent Structure (epo) Patents (Class 257/E21.628)
  • Patent number: 7241703
    Abstract: A method of forming films in a semiconductor device that can appropriately control a resistance value of a thin film resistance on an ozone TEOS film while preventing a metal thin film from remaining around a surface step unit after the metal thin film was dry etched. First, as shown in FIG. 1A, a step unit with the height of about 1 ?m is formed by forming elements such as HBT on a semiconductor substrate made up of semi-insulating GaAs. Next, as shown in FIG. 1B, a first ozone TEOS film with the thickness of 900 nm by a Normal pressure CVD method using mixed gas of tetraethoxysilane with ozone. Then, a second ozone TEOS film with the thickness of 100 nm is formed by reducing the ozone concentration to 10 g/m3, while maintaining the substrate temperature at 350° C.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Hikita, Yasuhiro Uemoto
  • Patent number: 7153781
    Abstract: In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the AA and STI are different, the improvement comprising: a) etching a gate silicide layer+a poly Si 2 layer; b) forming a continuous poly Si passivation layer on sidewalls of the silicide and poly Si 2 layers and at the interface of the poly Si 2 layer and a poly Si 1 layer and affecting thermal oxidation to form an underlying thin Si oxide gate layer; c) affecting a Si oxide breakthrough etch to clear the passivation layer at interface of the poly Si 2 and the poly Si 1 layers while leaving intact the passivation layer on the sidewalls of the silicide and the poly Si 2 layers; and d) etching the poly Si 1 layer with an oxide selective process to preserve the underlying thin gate oxide and thin passivation layer at the sidewall to obtain vertical profiles of poly Si gate stacks both at the AA and the STI oxide.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: December 26, 2006
    Assignee: Infineon Technologies AG
    Inventors: Heon Lee, Young-Jin Park