Abstract: A semiconductor device (20, 21, 22), including: a channel region (4) of a first conductivity type formed at a surface layer portion of a semiconductor substrate (1); a source region (25) of a second conductivity type which is different from the first conductivity type, the source region (25) being formed at a rim of a trench (17) having a depth sufficient to penetrate through the channel region (4); a drain region (2) of the second conductivity type formed at a region adjacent to a bottom of the trench (17); a gate insulating film (13) formed along an inner side wall of the trench (17); a gate electrode (26, 36) arranged in the trench (17) so as to be opposed to the channel region (4) with the gate insulating film (13) interposed therebetween; a conductive layer (37, 40, 40a, 40b) formed in the trench (17) so as to be nearer to the drain region (2) than the gate electrode (26, 36); and an insulating layer (15) surrounding the conductive layer (37, 40, 40a, 40b) to electrically insulate the conductive layer (3

Abstract: According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.

Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.

Abstract: A trench type power MOSFET has a thin vertical gate oxide along its side walls and a thickened oxide with a rounded bottom at the bottom of the trench to provide a low RDSON and increased VDSMAX and VGSMAX and a reduced Miller capacitance. The walls of the trench are first lined with nitride to permit the growth of the thick bottom oxide to, for example 1000 ? to 1400 ? and the nitride is subsequently removed and a thin oxide, for example 320 ? is regrown on the side walls. In another embodiment, the trench bottom in amorphized and the trench walls are left as single crystal silicon so that oxide can be grown much faster and thicker on the trench bottom than on the trench walls during an oxide growth step. A reduced channel length of about 0.7 microns is used. The source diffusion is made deeper than the implant damage depth so that the full 0.7 micron channel is along undamaged silicon.