Abstract: Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation layer can be kept thin, and the threshold voltage of a nonvolatile memory cell including the floating gate can be increased. As a result, the endurance of the tunnel insulation layer and the data retention characteristics of the nonvolatile memory cell is improved.

Abstract: A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure.

Abstract: Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a method of manufacturing a semiconductor device includes a exposing a first photo resist layer using a first light beam thereby forming first features. The first exposure is performed by the first light beam passing through a first dipole illuminator and then a first mask. A dipole axis of the first dipole illuminator is oriented in a first direction. After exposing the first photo resist layer, forming second features using a second exposure with a second light beam. The second exposure is performed by the second light beam passing through a second dipole illuminator and then a second mask. A dipole axis of the second dipole illuminator is oriented in a second direction. The first direction and the second direction are not perpendicular. The first and the second features comprise a pattern for forming contact holes.

Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

Abstract: Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.

Abstract: A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.

Abstract: Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer layers are formed on both sides of the gate stack and a portion of the second region. Landing plugs are formed on the contact hole, a portion of the semiconductor substrate exposed by a thickness of the spacer layer, and a lateral side of the trench. A second interlayer dielectric is formed to separate the landing plug. The bit line contact plug is connected to a first portion of the landing plug that extends to the lateral side of the trench. The bit line stack is connected to the bit line contact plug. The storage node contact plug is connected to the first portion and a second portion of the landing plug located at a corresponding position in a diagonal direction.

Abstract: A manufacturing method of a volatile memory device is provided. The manufacturing method includes steps as follows. A sacrificial layer is formed in an area which is predetermined for forming a metal gate. Then, a thermal treatment process or other high temperature processes are performed in a peripheral circuit region. Next, a fabricating process of the metal gate is performed. Thus, the volatile memory device which has a lower contact resistance and a higher driving ability of the device can be produced, and thereby poor thermal stability and pollution of metal diffusion can be avoided.

Abstract: An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried capacitive elementary trench forming the elementary storage capacitor, and an elementary well located above the lower region of the substrate and isolated laterally by a lateral electrical isolation region. The elementary active component is located in the elementary well or in and on the elementary well. The capacitive elementary trench is located under the elementary active component and is in electrical contact with the elementary well. In one preferred embodiment, the lateral electrical isolation region is formed by a trench filled with a dielectric material and has a greater depth than that of the elementary well. Also provided is a method for fabricating an integrated circuit that includes a semiconductor device for storing charge.

Abstract: Method for fabricating a self-aligned gate of a transistor including: forming a plurality of deep trench capacitors in a substrate, concurrently forming a surface strap and a contact pad on a surface of the substrate, wherein a spacing between the surface strap and the contact pad exposes a portion of an active area, filling the spacing with a dielectric layer, forming a photoresist pattern on the substrate, wherein the photoresist has an opening situated directly above the spacing between the surface strap and the contact pad, etching away the dielectric layer and a portion of a shallow trench isolation region through the opening thereby forming an upwardly protruding fin-typed channel structure, forming a gate dielectric layer on the upwardly protruding fin-typed channel structure, and forming a gate on the gate dielectric layer.

Abstract: A memory gain cell for a memory circuit, a memory circuit formed from multiple memory gain cells, and methods of fabricating such memory gain cells and memory circuits. The memory gain cell includes a storage device capable of holding a stored electrical charge, a write device, and a read device. The read device includes a fin of semiconducting material, electrically-isolated first and second gate electrodes flanking the fin, and a source and drain formed in the fin adjacent to the first and the second gate electrodes. The first gate electrode is electrically coupled with the storage device. The first and second gate electrodes are operative for gating a region of the fin defined between the source and the drain to thereby regulate a current flowing from the source to the drain. When gated, the magnitude of the current is dependent upon the electrical charge stored by the storage device.

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.

Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.

Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.