Source Or Drain Doping Programmed (epo) Patents (Class 257/E21.673)
  • Patent number: 8455342
    Abstract: A mask ROM fabrication method which comprises steps: sequentially forming a gate dielectric layer and a first photoresist layer on a substrate; letting a light having a wavelength of 365 nm pass through a first phase shift mask to photolithographically form on the first photoresist layer a plurality of first trenches having a width of 243-365 nm; doping the substrate to form a plurality of embedded bit lines having a width of 243-365 nm; removing the first photoresist layer; sequentially forming a polysilicon layer and a second photoresist layer on the gate dielectric layer; and letting the light pass through a second phase shift mask to photolithographically form a plurality of polysilicon word lines on the polysilicon layer. Thereby is reduced the line width of mask ROM to 243-365 nm and decreased the area of mask ROM.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: June 4, 2013
    Assignees: Nyquest Technology Corporation Limited, Nuvoton Technology Corporation
    Inventors: Kuang-Chu Chen, Cheng Tao Chen, Chung-Lung Hsu, Chun-Yao Chiu, Chin-Yung Chang
  • Patent number: 7777256
    Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Young-Ho Kim, Myung-Jo Chun, Jung-Ho Moon
  • Patent number: 7704825
    Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: April 27, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Kouichi Yamada
  • Patent number: 7075137
    Abstract: In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations (7) that are widened for division into slices. Instead of this, the interconnects present below a bit line may be omitted or two mutually adjacent bit lines (41, 42) may be wired up in such a way that the memory transistors present between them operate only in the dummy mode.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: July 11, 2006
    Assignees: Infineon Technologies AG, Infineon Technologies Flash GmbH & Co. KG
    Inventors: Josef Willer, Christoph Ludwig, Joachim Deppe