Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.

Abstract: Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.

Abstract: Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.

Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.

Abstract: Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device.

Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.

Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.

Abstract: The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an -shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.

Abstract: The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.

Abstract: Monolithic three dimensional NAND strings and methods of making. The method includes both front side and back side processing. Using the combination of front side and back side processing, a NAND string can be formed that includes an air gap between the floating gates in the NAND string. The NAND string may be formed with a single vertical channel. Alternatively, the NAND string may have a U shape with two vertical channels connected with a horizontal channel.

Abstract: In a semiconductor device using a nonvolatile memory, high speed erasing operation and low power consumption are realized. In a nonvolatile memory in which a channel formation region, a tunnel insulating film, and a floating gate are stacked in this order, the channel formation region is formed using an oxide semiconductor layer. In addition, a metal wiring for erasing is provided in a lower side of the channel formation region so as to face the floating gate. With the above structure, when erasing operation is performed, charge accumulated in the floating gate is extracted to the metal wiring through the channel formation region. Consequently, high speed erasing operation and low power consumption of the semiconductor device can be realized.

Abstract: A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

Abstract: A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material.

Abstract: A method is provided for enhancing charge storage in an E2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage element formed over the substrate channel region and separated therefrom by gate dielectric material, a conductive control gate that is separated from the charge storage element by intervening dielectric material, and a conductive heating element disposed in proximity to the charge storage element. The method comprises performing a programming operation that causes charge to be placed on the charge storage element and, during the programming operation, heating the heating element to a temperature such that heat is provided to the charge storage element.

Abstract: A method of making a uniform nanoparticle array, including performing diblock copolymer thin film self assembly over a first dielectric on silicon, creating a porous polymer film, transferring a pattern into the first dielectric, selectively growing epitaxial silicon off a silicon substrate from within pores to create a silicon nanoparticle array.

Abstract: A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film.

Abstract: Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Abstract: A method of manufacturing a flash memory device having an enhanced gate coupling ratio includes steps of forming a first semiconductor layer on a substrate and forming a semiconductor spacer layer on top of the first semiconductor layer. The semiconductor spacer layer includes a plurality of recesses. The method provides a semiconductor spacer structure which functions to increase the contact area between a floating gate and a control gate of the flash memory device.

Abstract: A semiconductor device and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer and the second conductive layer are patterned. A first passivation layer is formed on sidewalls of the gate electrode layer. Gate patterns are formed by etching the dielectric layer, the first conductive layer, and the tunnel dielectric layer, which have been exposed. A second passivation layer is formed on the entire surface along a surface of the gate patterns including the first passivation layer.

Abstract: A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.

Abstract: A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Abstract: Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

Abstract: A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.

Abstract: A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.

Abstract: A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a larger height than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract: A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.

Abstract: A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed.

Abstract: Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

Abstract: An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer forming a floating gate. The first polysilicon layer is horizontally disposed in series with the second polysilicon layer and is connected to the third polysilicon layer, so that the control gate encloses all of the floating gate except for a tunnel surface of the floating gate.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: Methods of fabricating a dual control gate non-volatile memory array are described. Parallel strips of floating gate material are formed over the substrate in a first direction but separated from it by a tunnel dielectric. In the gaps between these strips control gate material is formed forming a second set of parallel strips but insulated from both the adjacent floating gate stripes and the substrate. Both sets of strips are isolated in a second direction perpendicular to the first direction forming an array of individual floating gates and control gates. The control gates formed from an individual control gate strip are then interconnected by a conductive wordline such the potential on individual floating gates are controlled by the voltages on two adjacent wordlines. In other variations either the floating gates or the control gates may be recessed into the original substrate.

Abstract: Example embodiments include nonvolatile memory devices that have good operation performance and may be made in a highly integrated structure, and methods of operating the same. Example embodiments of the nonvolatile memory devices include a substrate electrode, and a semiconductor channel layer on the substrate electrode, a floating gate electrode on the substrate electrode, wherein a portion of the floating gate electrode faces the semiconductor channel layer, a control gate electrode on the floating gate electrode, and wherein a distance between a portion of the floating gate electrode and the substrate electrode is smaller than a distance between the semiconductor channel layer and the substrate electrode wherein charge tunneling occurs.

Abstract: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the injector layer. A polysilicon control gate formed over the high dielectric constant layer. The cell can be formed in a planar architecture or a two element, split channel, three-dimensional device. The planar cell is formed with the high dielectric constant layer and the control gate being formed over and substantially around three sides of the embedded trap layer. The split channel device has a source line in the substrate under each trench and a bit line on either side of the trench.

Abstract: A floating gate MOS transistor having a conductive floating gate electrode insulated from a semiconductor material having a main surface by a gate dielectric layer. At least one isolation region formed lateral to the gate electrode. An evacuation is formed in the isolation region and beneath the main surface of the semiconductor material layer. A conductive material fills the evacuation. A conductive control gate electrode is formed above the floating gate electrode. The floating gate electrode is laterally aligned to at least one isolation region.

Abstract: The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

Abstract: A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material.

Abstract: A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.

Abstract: A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.

Abstract: An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to form a plurality of first gates. An oxidation process is performed to form an oxide layer on the sidewalls of the first gates. The patterned mask layer is removed. A plurality of second gates is formed between two adjacent first gates so that the first gates and the second gates co-exist to form a memory cell column. A doped region is formed in the substrate adjacent to the memory cell column.

Abstract: A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Abstract: An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.

Abstract: A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen.

Abstract: The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the injector layer. A polysilicon control gate formed over the high dielectric constant layer. The cell can be formed in a planar architecture or a two element, split channel, three-dimensional device. The planar cell is formed with the high dielectric constant layer and the control gate being formed over and substantially around three sides of the embedded trap layer. The split channel device has a source line in the substrate under each trench and a bit line on either side of the trench.

Abstract: A semiconductor memory device includes select transistors, cell transistors, and cell units. The select transistors formed on a substrate and include first electrodes. The cell transistors include second electrodes with a charge storage layer and a control. The cell units including a plurality of the cell transistors connected together in series between the two select transistors. A distance between the first electrodes and a distance between the first electrodes which is adjacent to the second electrodes and adjacent second electrodes are each at least double a distance between second electrodes. A surface of the substrate between second electrodes is flush with the surface of the substrate between the first electrode and the adjacent second electrodes. The surface of the substrate between the first electrodes is positioned lower than the surface of the substrate between the first electrodes and the second electrodes.

Abstract: Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips.