Abstract: A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: A semiconductor device includes a first insulated gate field effect transistor, a second insulated gate field effect transistor, a bipolar transistor, a first element isolation structure formed on a main surface above a pn junction formed between an emitter region and a base region, a second element isolation structure formed on the main surface above a pn junction formed between the base region and a collector region, and a third element isolation structure formed on the main surface opposite to the second element isolation structure relative to the collector region, in which the semiconductor device further includes a bipolar dummy electrode formed on at least one of the first element isolation structure, the second element isolation structure and the third element isolation structure and having a floating potential.

Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).

Abstract: An epilayer structure includes a field-effect transistor structure and a heterojunction bipolar transistor structure. The heterojunction bipolar transistor structure contains an n-doped subcollector and a collector formed in combination with the field-effect transistor structure, wherein at least a portion of the subcollector or collector contains Sn, Te, or Se. In one embodiment, a base is formed over the collector; and an emitter is formed over the base. The bipolar transistor and the field-effect transistor each independently contain a III-V semiconductor material.

Abstract: A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: Method for manufacturing a semiconductor device. A channel layer is formed by epitaxially growing a semiconductor layer, in which an ion species of a first conductivity is implanted on a semiconductor substrate. A source region, a drain region, and an emitter region which are of the first conductivity, are formed by activating, using annealing, a portion of the semiconductor substrate in which the ion species has been implanted. An emitter layer of the first conductivity, a base layer of a second conductivity having a band gap smaller than a band gap of the emitter layer, and a collector layer of the first conductivity or a non-doped collector layer are sequentially and epitaxially grown on the channel layer.

Abstract: In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source region with striations of alternating n-type and p-type material radiating outwardly from the pad to the source to provide for an adjustable snapback voltage.

Abstract: A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate FET in a first region of a semiconductor base and a trench element-isolation layer in a second region of the semiconductor base, simultaneously. The second step is the step of forming a first diffusion layer of the insulated-gate FET on a side of the trench gate and a second diffusion layer of the electronic element in a region surrounded by the trench element-isolation layer, simultaneously. The third step is the step of forming a third diffusion layer of the insulated-gate FET in the first diffusion layer and a fourth diffusion layer of the electronic element in the second diffusion layer, simultaneously.

Abstract: Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: A method of fabricating an integrated BiCMOS circuit is provided, the circuit including bipolar transistors 10 and CMOS transistors 12 on a substrate. The method comprises the step of forming an epitaxial layer 28 to form a channel region of a MOS transistor and a base region of a bipolar transistor. Growing of the epitaxial layer includes growing a first sublayer of silicon 28a, a first sublayer of silicon-germanium 28b onto the first sublayer of silicon, a second sublayer of silicon 28c onto the first sublayer of silicon-germanium, and a second sublayer of silicon-germanium 28d onto the second sublayer of silicon. Furthermore, an integrated BiCMOS circuit is provided, which includes an epitaxial layer 28 as described above.

Abstract: A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate FET in a first region of a semiconductor base and a trench element-isolation layer in a second region of the semiconductor base, simultaneously. The second step is the step of forming a first diffusion layer of the insulated-gate FET on a side of the trench gate and a second diffusion layer of the electronic element in a region surrounded by the trench element-isolation layer, simultaneously. The third step is the step of forming a third diffusion layer of the insulated-gate FET in the first diffusion layer and a fourth diffusion layer of the electronic element in the second diffusion layer, simultaneously.

Abstract: An amplifier integrated circuit element or J-FET is used for impedance conversion and amplification of ECM. The amplifier integrated circuit element has advantages of allowing an appropriate gain to be set by adjusting a circuit constant, and of producing a higher gain than the J-FET; but also has a problem of having a complicated circuit configuration and requiring high costs. Using only the J-FET has also problems of outputting a voltage insufficiently amplified and producing a low gain. Against this background, provided is a discrete element in which: a J-FET and a bipolar transistor are integrated on one chip; a source region of the J-FET is connected to a base region of the bipolar transistor; and a drain region of the J-FET is connected to a collector region of the bipolar transistor. Accordingly, an ECM amplifying element with high input impedance and low output impedance can be achieved.

Abstract: Provided are bipolar transistor, BiCMOS device and method of fabricating thereof, in which an existing sub-collector disposed beneath a collector of a SiGe HBT is removed and a collector plug disposed at a lateral side of the collector is approached to a base when fabricating a Si-based very high-speed device, whereby it is possible to fabricate the SiGe HBT and an SOI CMOS on a single substrate, reduce the size of the device and the number of masks to be used, and implement the device of high density, low power consumption, and wideband performance.

Abstract: The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with—interposed between said source and drain regions—a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2).

Abstract: The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.

Abstract: A structure and method of fabricating the structure. The structure including: a dielectric isolation in a semiconductor substrate, the dielectric isolation extending in a direction perpendicular to a top surface of the substrate into the substrate a first distance, the dielectric isolation surrounding a first region and a second region of the substrate, a top surface of the dielectric isolation coplanar with the top surface of the substrate; a dielectric region in the second region of the substrate; the dielectric region extending in the perpendicular direction into the substrate a second distance, the first distance greater than the second distance; and a first device in the first region and a second device in the second region, the first device different from the second device, the dielectric region isolating a first element of the second device from a second element of the second device.

Abstract: An integrated circuit device can include at least one bipolar junction transistor (BJT) having a first base electrode comprising a semiconductor material doped to a first conductivity type formed on and in contact with a surface of the semiconductor substrate, and separated from an emitter electrode by a separation space. A first base region can be formed in the substrate below the emitter electrode and include a first portion of the substrate doped to the first conductivity type. A second base region can be formed in the substrate below the separation space and can include a second portion of the substrate doped to the first conductivity type.

Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.

Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Abstract: A BiCMOS integrated circuit (IC) includes a floating gate-type non-volatile memory (NVM) device that uses the polycrystalline silicon gate of a CMOS FET and the P-base and N-emitter diffusions of a bipolar transistor to provide an isolated P-type body and N-type source/drain diffusions. The P-body diffusion of the NVM device is isolated from a P-substrate by an N-well, thus facilitating the use of reduced positive and negative voltage levels to produce the onset of Fowler-Nordheim tunneling without the need for a triple-well structure. The polysilicon gate structure is formed on a suitable gate oxide over the P-body. The source/drain diffusions, which like the N-emitter diffusions of the bipolar transistor have no LDD, produce a reduced field drop across the gate oxide to allow Fowler-Nordheim tunneling from the source side.

Abstract: Method and systems for producing a semiconductor circuit arrangement are disclosed. In one implementation, after a formation of a first electrically conductive layer at the surface of a semiconductor substrate for the purpose of realizing a base connection layer and a first split gate layer, an implantation mask is formed for the purpose of carrying out a first collector implantation for the purpose of forming a collector connection zone. After the formation of a hard mask layer and a first etching mask, the hard mask layer is patterned and an emitter window is uncovered using the patterned hard mask layer. Using the patterned hard mask layer a second collector implantation is effected for the purpose of forming a collector zone, a base layer being formed in the region of the emitter window.