Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

Abstract: A semiconductor processing component has an outer surface portion comprised of silicon carbide, the outer surface portion having a skin impurity level and a bulk impurity level. The skin impurity level is average impurity level from 0 nm to 100 nm of depth into the outer surface portion, the bulk impurity level is measured at a depth of at least 3 microns into the outer surface portion, and the skin impurity level is not greater than 80% of the bulk impurity level.

Abstract: There are provided a semiconductor substrate; a photoelectric conversion film stacked on a layer that is disposed on the light incidence side of the semiconductor substrate; signal reading unit formed in a surface portion of the semiconductor substrate, for reading out, as shot image signals, signals corresponding to signal charge amounts detected by the photoelectric conversion film according to incident light quantities; a transparent substrate bonded to a layer that is disposed on the light incidence side of the photoelectric conversion film with a transparent resin as an adhesive; and electric connection terminals which are connected to the signal reading unit by interconnections and which penetrate through the semiconductor substrate and are exposed in a surface, located on the opposite side to the side where the photoelectric conversion film is provided, of the semiconductor substrate.

Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

Abstract: A method for manufacturing a pixel structure includes providing a substrate including a transistor region and a pixel region, forming at least one gate electrode on the transistor region, forming an insulating layer on the substrate to overlay the gate electrode, and forming a patterned semi-conductive layer on the surface of a portion of the insulating layer disposed on the transistor region and the pixel region. A patterned first protective layer is formed on a portion of the patterned semi-conductive layer corresponding to the gate electrode, and the patterned semi-conductive layer is doped without being overlaid by the patterned first protective layer.

Abstract: A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration.

Abstract: An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.

Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.

Abstract: A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern.

Abstract: A substrate 1 for growing nitride semiconductor has a first and second face and has a thermal expansion coefficient that is larger than that of the nitride semiconductor. At least n-type nitride semiconductor layers 3 to 5, an active layer 6 and p-type nitride semiconductor layers 7 to 8 are laminated to form a stack of nitride semiconductor on the first face of the substrate 1. A first bonding layer including more than one metal layer is formed on the p-type nitride semiconductor layer 8. A supporting substrate having a first and second face has a thermal expansion coefficient that is larger than that of the nitride semiconductor and is equal or smaller than that of the substrate 1 for growing nitride semiconductor. A second bonding layer including more than one metal layer is formed on the first face of the supporting substrate. The first bonding layer 9 and the second bonding layer 11 are faced with each other and, then, pressed with heat to bond together.

Abstract: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.

Abstract: An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.

Abstract: An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.