Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

Abstract: A semiconductor storage device according to an embodiment includes a substrate, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a first surface contacting with the substrate, a second surface on an opposite side to the first surface, and a first pad provided on the second surface. The second semiconductor chip includes a third surface contacting with the second surface, a fourth surface on an opposite side to the third surface, and a cutout portion. The cutout portion is provided at a corner portion where the third surface crosses a lateral surface between the third surface and the fourth surface. The cutout portion overlaps with at least a part of the first pad as viewed from above the fourth surface.

Abstract: The disclosed technique may be used to electrically and physically connect semiconductor wafers. The wafer may utilize a thick dielectric. Indium bumps may be deposited and patterned in a dielectric film with a small diameter, tall height and substantially uniform in size and shape. The indium can be melted to create small grain size and uniform height bumps. The dielectric film may feature trenches around the indium bumps to prevent shorting of pixels when pressed together.

Abstract: The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip.

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

Abstract: The present technology relates to a solid-state imaging device that can reduce the number of steps and enhance mechanical strength, a method of manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device includes a laminate including a first semiconductor substrate having a pixel region and at least one second semiconductor substrate having a logic circuit, the at least one second semiconductor substrate being bonded to the first semiconductor substrate such that the first semiconductor substrate becomes an uppermost layer, and a penetration connecting portion that penetrates from the first semiconductor substrate into the second semiconductor substrate and connects a first wiring layer formed in the first semiconductor substrate to a second wiring layer formed in the second semiconductor substrate. The first wiring layer is formed with Al or Cu. The present technology is applicable, for example, to a back-surface irradiation type CMOS image sensor.

Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.

Abstract: A bonding method is capable of realizing high bonding strength and connection reliability even at a connection part in a high temperature area by means of simple operation low temperature bonding. The method includes a first step wherein, on at least one of the bonded surfaces of two materials to be bonded having a smooth surface, a thin film of noble metal with a volume diffusion coefficient greater than that of the base metal of the material to be bonded is formed using an atomic layer deposition method at a vacuum of 1.0 Pa or higher, a second step wherein a laminate is formed by overlapping the two materials to be bonded so that the bonded surfaces of the two materials are connected through the thin film, and a third step wherein the two materials to be bonded are bonded by holding the laminate at a predetermined temperature.

Abstract: A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal be is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.

Abstract: A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, divider walls are arranged in a pattern on a first surface of a device wafer such that regions between the divider walls define mounting sites. Die stacks are mounted to the device wafer, wherein individual die stacks are located at a corresponding mounting site between the divider walls. The device wafer is cut through from a second surface that is opposite the first surface of the device wafer, and the divider walls are removed from between the die stacks to form a vacant lane between adjacent die stacks.

Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pat

Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

Abstract: A circuit board includes at least two circuit board units stacked together. Each circuit board unit includes a substrate and a circuit layer. The substrate defines a conductive hole penetrating therethrough. The conductive hole provided with a conductor therein. One side of the substrate further defines a groove, the groove including a concave portion aligned with the conductive hole. The circuit layer includes a connection pad located in the concave portion. The connection pad is shaped as a conductive protrusion, which surrounds and is electrically connected to the conductor. The circuit layer is located in the groove, and the conductive hole is electrically connecting the circuit layers of the circuit board units.

Abstract: A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.

Abstract: A connection arrangement for forming a component carrier structure is disclosed. The connection arrangement includes a first electrically conductive connection element and a second electrically conductive connection element. The first connection element and the second connection element are configured such that, upon connecting the first connection element with the second connection element along a connection direction, a form fit is established between the first connection element and the second connection element that limits a relative motion between the first connection element and the second connection element in a plane perpendicular to the connection direction. A component carrier and a method of forming a component carrier structure are also disclosed.

Abstract: A display device includes a display substrate comprising a polymer layer including a first non-bending area, a second non-bending area that overlaps the first non-bending area when viewed in a plan view, and a bending area arranged between the first non-bending area and the second non-bending area. A display element layer is disposed on the polymer layer. A plurality of signal pad groups is disposed in the second non-bending area and is configured to be electrically connected to the display element layer. An upper substrate is disposed on a top surface of the display substrate. A flexible circuit board comprising a plurality of connection pad groups is arranged in correspondence to the signal pad groups. An area of the upper substrate is larger than an area of the display substrate when viewed in a plan view.

Abstract: A semiconductor device includes an insulating substrate, a wiring, a semiconductor chip and a resin layer. The wiring is provided on the insulating substrate. The wiring board includes (i) an insulating material and (ii) a pad exposed relative to the insulating material and electrically connected to the wiring. A height of the insulating material in a vertical direction of the wiring board varies along the wiring board. The semiconductor chip includes a bump connected to the pad on a first surface of the semiconductor chip. The resin layer covers a periphery of the bump between the wiring board and the semiconductor chip.

Abstract: A method for fabricating a semiconductor device includes providing a base wafer comprising a scribing portion; bonding a first stacked die and a second stacked die onto a front surface of the base wafer through a hybrid bonding process; conformally forming a re-fill layer to cover the first stacked die and the second stacked die; forming a first molding layer to cover the re-fill layer and configure an intermediate semiconductor device comprising the base wafer, the first stacked die, the second stacked die, the re-fill layer, and the first molding layer; and dicing the intermediate semiconductor device along the scribing portion to separate the first stacked die and the second stacked die, the re-fill layer, the first molding layer, and the base wafer.

Abstract: A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.

Abstract: A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

Abstract: A mirror for extreme ultraviolet light includes: a substrate (41); a multilayer film (42) provided on the substrate and configured to reflect extreme ultraviolet light; and a capping layer (53) provided on the multilayer film, and the capping layer includes a first layer (61) containing an oxide of a metal, and a second layer (62) arranged between the first layer and the multilayer film and containing at least one of a boride of the metal and a nitride of the metal.

Abstract: A fingerprint sensing module comprising a fingerprint sensor device having a sensing array arranged on a first side of the device, the sensing array comprising an array of fingerprint sensing elements. The fingerprint sensor device comprises connection pads for connecting to external circuitry. The fingerprint sensing module further comprises a fingerprint sensor device cover structure, arranged to cover the fingerprint sensor device, having a first side configured to be touched by a finger, thereby forming a sensing surface of the sensing module, and a second side facing the sensing array, wherein the cover structure comprises conductive traces for electrically connecting the fingerprint sensor module to external circuitry, and wherein a surface area of the cover structure is larger than a surface area of the sensor device. The fingerprint sensor device comprises wire-bonds electrically connecting the connection pads of the fingerprint sensing device to the conductive traces of the cover structure.

Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

Abstract: Disclosed are a die bonding apparatus, a substrate bonding apparatus, a die bonding method, and a substrate bonding method that are capable of bonding a die to a substrate or bonding substrates together without using a bonding medium such as an adhesion film and a solder bump. The die bonding method includes hydrophilizing a bonding surface of the die, by plasma processing, forming a liquid film on a bonding area of the substrate, by supplying a liquid including water to the bonding area of the substrate, pre-bonding the die to the substrate by bringing the die into contact with the liquid film, and post-bonding one or more dies to the substrate at the same time, by performing heat treatment in a state in which the one or more dies are pre-bonded to the substrate.

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Abstract: Disclosed are a method for manufacturing a support frame structure and a support frame structure. The method includes steps of: providing a metal plate including a support region and an opening region; forming an upper dielectric hole and a lower dielectric hole respectively at an upper surface and a lower surface of the support region by photolithography, with a metal spacer connected between the upper dielectric hole and the lower dielectric hole; forming an upper metal pillar on an upper surface of the metal plate, and laminating an upper dielectric layer which covers the upper metal pillar and the upper dielectric hole; etching the metal spacer, forming a lower metal pillar on the lower surface of the metal plate, and laminating a lower dielectric layer which covers the lower metal pillar and the lower dielectric hole.

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.

Abstract: A MEMS transducer for interacting with a volume flow of a fluid includes a substrate which includes a layer stack having a plurality of layers which form a plurality of substrate planes, and which includes a cavity within the layer stack. The MEMS transducer includes an electromechanical transducer connected to the substrate within the cavity and including an element which is deformable within at least one plane of movement of the plurality of substrate planes, deformation of the deformable element within the plane of movement and the volume flow of the fluid being causally correlated. The MEMS transducer includes an electronic circuit arranged within a layer of the layer stack, the electronic circuit being connected to the electromechanical transducer and being configured to provide a conversion between a deformation of the deformable element and an electric signal.

Abstract: Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.

Abstract: A method for packaging a chip and a chip packaging structure. A passivation layer is provided on bonding pads of a wafer, a first metal bonding layer is formed on the passivation layer, and a second metal bonding layer is formed on a substrate. The substrate and the wafer are bonded via the first metal bonding layer and the second metal bonding layer, and are packaged as a whole. A first shielding layer is provided on the substrate, and the first shielding layer is in contact with the second metal bonding layer. After the wafer and the substrate are bonded, the wafer is subject to half-cutting to expose the first metal bonding layer. Then, the second shielding layer electrically connected to the first metal bonding layer is formed.

Abstract: A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.

Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.

Abstract: Provided is a semiconductor package including: at least two pads, a first substrate, at least two semiconductor devices, a second substrate, an electrical connection part, and a package housing, wherein the at least two pads are electrically or structurally separated from each other, the first substrate is formed of leads spaced apart from the pads, the at least two semiconductor devices are bonded on each of the pads, the second substrate is formed on and spaced apart from the upper parts of the semiconductor devices, is placed on and electrically connected to the at least one lead of the first substrate, and includes at least one penetrated opening unit on an area facing the at least one semiconductor device, the electrical connection part electrically connects the at least one semiconductor device with the second substrate, and the package housing covers the semiconductor devices and the electrical connection part. Accordingly, the semiconductor package has a multi die structure and is compact.

Abstract: One or more stud bumps may form a conductive column to a component having back side metallization. In an embodiment, the column of stud bumps may be about 130 um vertically (Z-direction). Providing a microelectronics package with a column of stud bumps electrically connected to a component having back side metallization may provide a cost effective electrical interconnect and may enable the incorporation of components of different thicknesses, including that the component thicknesses are independent of each other, in a single fanout package, while providing a thin package profile and back side surface finish integration.

Abstract: Disclosed is a method for fabricating a semiconductor package. A mold press with upper and lower chases is used. A molded underfill (MUF) material is dispensed on a bottom surface of a mold cavity to form a first dispensed pattern with a serpentine shape. A base substrate on which die stacks are mounted is loaded on the upper chase. The mold cavity in which the die stacks are inserted is closed and MUF material flows between the die stacks to impregnate the die stacks.

Abstract: A mounting method is a method for mounting a diced semiconductor chip having a first face that is held on a carrier substrate and a second face that is an opposite face of the first face on a circuit board placed on a mounting table. The mounting method includes affixing the second face of the semiconductor chip to an adhesive sheet, removing the carrier substrate from the semiconductor chip, reducing an adhesive strength of the adhesive sheet, and mounting the semiconductor chip on the circuit board by holding a first face side of the semiconductor chip with a head to separate the semiconductor chip from the adhesive sheet, and joining a second face side of the semiconductor chip to the circuit board.

Abstract: A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

Abstract: A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

Abstract: An image sensor package includes a plastic packaging structure; and a transparent plastic window disposed in the plastic packaging structure, wherein material of the transparent plastic window includes plastic and an additive, and the additive is selected from the group consisting of germanium, silicon, potassium bromide, potassium chloride, sodium chloride, zinc sulfide, and zinc selenide.

Abstract: A method for measuring chips bonding strength includes steps as follows: An auxiliary pattern is formed on a first surface of a first chip. A second surface of a second chip is bonded to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, dimensions of the at least one gap space and the auxiliary pattern are measure respectively; and the bonding strength between the first chip and the second chip is estimated according to the dimensions.

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

Abstract: The invention, which relates to the technical field of inductance embedding, specifically discloses an embedded circuit board. The embedded circuit board includes: at least layer of sub-body, where preset positions of the sub-bodies are provided with through slots; and an inductance element embedded within the slots and configured to be spaced apart from sidewalls of the slots. In the above manner, it is possible to make the embedded circuit board of the present application structurally compact, highly integrated, widely applicable, and safe and reliable.

Abstract: Components may be placed on an active side of a wafer as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer may be passivation-defined by forming a conductive terminal over a first dielectric layer and a forming a passivating, second dielectric layer over the conductive terminal. Openings formed in the second dielectric layer define component contacts to the conductive terminal and circuitry on the wafer coupled to the conductive terminal. Trenches may be used between pairs of contact pads to further reduce issues resulting from short circuits and/or underfills. A conductive pad may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer.

Abstract: A semiconductor device comprises two memory chips, one control chip controlling each memory chip, a signal transmission path through which a signal transmission between the control chip and each memory chip is performed, and a capacitance coupled onto the signal transmission path. Also, the capacitance (capacitor element) is larger than each parasitic capacitance parasitic on each chip. Accordingly, it is possible to perform the signal transmission of the semiconductor device at high speed.

Abstract: A radio-frequency device comprises a radio-frequency chip, a first connecting element arranged over a chip surface of the radio-frequency chip, the first connecting element being designed to mechanically and electrically connect the radio-frequency chip to a circuit board, and a radio-frequency signal carrying element arranged over the chip surface and electrically coupled to the radio-frequency chip, the radio-frequency signal carrying element being covered by an electrically nonconductive material and being designed to transmit a signal in a direction parallel to the chip surface, wherein the first connecting element and the radio-frequency signal carrying element are arranged at a same level in relation to a direction perpendicular to the chip surface, and wherein the first connecting element is spaced apart from the radio-frequency signal carrying element by way of a region that is free of the electrically nonconductive material.

Abstract: A semiconductor assembly includes a carrier element with a first carrier element conductor path, a semiconductor chip, an electrically insulating element having a first insulating element conductor path, and a first spacer element. The semiconductor chip is connected electrically and mechanically on a first semiconductor side via a first connecting material to the first carrier element conductor path. The semiconductor chip is connected on a second semiconductor side, which faces away from the first semiconductor side of the semiconductor chip, via a second connecting material to the first insulating element conductor path, which is arranged on a first insulating element side of the electrically insulating element. The first spacer element is arranged for maintaining a distance between the carrier element and an assembly element facing toward the second semiconductor side of the semiconductor chip and is connected mechanically to both the carrier element and the assembly element.

Abstract: A method, computer system, and computer program product for optimizing a number of robots for operation of a process at a target system. The method may include providing a plurality of available robots to carry out tasks in the process at the target system. The method may monitor the target system by carrying out the process or part of the process with a varying number of robots to determine the processor utilization whilst the robots are executing a varying number of tasks. The method may balance process constraints of the execution of the process with physical system constraints of the target system by measuring a relationship between a number of tasks at a transactional level and the processor utilization. The method may output the optimized number of robots to be allocated for the process or part of the process.