Abstract: The invention discloses a bionic laminated thermal insulation material, which imitates a multi-thin laminated and thin-layer micro-pore structure of Sequoia sempervirens bark with fire resistance, corrosion resistance and excellent thermal insulation performance. A low thermal conductivity microporous powder is used as main raw material, while reinforcing agent, plasticizer and porosity agent are added to form microporous thin-layer units, and each thin-layer unit is bonded and laminated to make a laminated thermal insulation material. The thermal conductivity of the finished products is as low as 0.02˜0.05 W/m·k, with good thermal insulation and mechanical properties, which can be used in a temperature range below 1000° C., with better thermal insulation and energy-saving effect and toughness than ordinary thermal insulation materials, significantly reducing the thickness of the insulation layer, and can be widely used in industrial furnaces, thermal engineering devices, insulation pipes and other fields.

Abstract: A glass ceramic sintered body having a small dielectric loss in a high frequency band of 10 GHz or higher and a wiring substrate using the same are provided. The glass ceramic sintered body contains crystallized glass, an alumina filler, and silica. The content of the crystallized glass is 45 mass % to 85 mass %, the content of the alumina filler is 14.8 mass % to 50.1 mass % in terms of Al2O3, and the content of silica is 0.2 mass % to 4.9 mass % in terms of SiO2.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

Abstract: The glass ceramic material of the present disclosure contains a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal, and a filler that contains quartz, Al2O3, and ZrO2. The glass ceramic material contains the glass in an amount of 57.4% by weight or more and 67.4% by weight or less, the quartz in the filler in an amount of 29% by weight or more and 39% by weight or less, the Al2O3 in the filler in an amount of 1.8% by weight or more and 5% by weight or less, and the ZrO2 in the filler in an amount of 0.3% by weight or more and 1.8% by weight or less.

Abstract: In a layered bonding material 10, a coefficient of linear expansion of a base material 11 is 5.5 to 15.5 ppm/K and a first surface and a second surface of the base material 11 are coated with pieces of lead-free solder 12a and 12b.

Abstract: A tinted glass composition and glass article including the same, the composition including: about 45 mol % to about 80 mol % SiO2; about 6 mol % to about 22 mol % Al2O3; 0 mol % to about 25 mol % B2O3; about 7 mol % to about 25 mol % of at least one alkaline earth oxide selected from MgO, CaO, SrO, BaO, and combinations thereof; about 0.5 mol % to about 20 mol % CuO; 0 mol % to about 6 mol % SnO2, SnO, or a combination thereof; 0 mol % to about 1.0 mol % C; 0 mol % to about 5 mol % La2O3; and 0 mol % to about 10 mol % PbO, and that is substantially free of alkali metal.

Abstract: The present invention relates to a conductive porous ceramic substrate and a method of manufacturing the same, and more particularly to a conductive porous ceramic substrate, in which a porous ceramic substrate used as a chuck or stage for fixing a thin semiconductor wafer substrate or display substrate through vacuum adsorption is imparted with antistatic performance so as to prevent the generation of static electricity, and a method of manufacturing the same.

Abstract: A monolithic substrate including a silica material fused to bulk copper is provided for coupling with electronic components, along with methods for making the same. The method includes arranging a base mixture in a die mold. The base mixture includes a bottom portion with copper micron powder and an upper portion with copper nanoparticles. The method includes arranging a secondary mixture on the upper portion of the base mixture. The secondary mixture includes a bottom portion with silica-coated copper nanoparticles and an upper portion with silica nanoparticles. The method includes heating and compressing the base mixture and the secondary mixture in the die mold at a temperature, pressure, and time sufficient to sinter and fuse the base mixture with the secondary mixture to form a monolithic substrate. The resulting monolithic substrate defines a first major surface providing thermal conductivity, and a second major surface providing an electrically resistive surface.

Abstract: A composite including an electrolyte layer containing solid oxide, and at least one electrode selected from a cathode disposed on one side of the electrolyte layer in a first direction and an anode disposed on the other side of the electrolyte layer in the first direction. Either one of two surfaces of the composite located on opposite sides in the first direction satisfies a first requirement that, as viewed in the first direction, a curvature determined on the basis of any three points juxtaposed at intervals of 5 mm is less than 0.0013 (l/mm) and that, as viewed in a second direction perpendicular to the first direction, the curvature is the reciprocal of the radius of an imaginary circle passing through the any three points.

Abstract: A ceramic wiring board that includes a ceramic insulator and a via-conductor. The ceramic insulator includes a crystalline constituent and an amorphous constituent. The via-conductor includes a metal and an oxide. The crystalline constituent and the oxide include at least one metal element in common. A tubular region having a thickness of 5 ?m adjoins and surrounds the via-conductor and has a higher concentration of the metal element than the ceramic insulator.

Abstract: A hermetic package of the present invention includes a package base and a glass cover hermetically sealed with each other via a sealing material layer, wherein the package base includes a base part and a frame part formed on the base part, wherein the package base has an internal device housed within the frame part, wherein the sealing material layer is arranged between a top of the frame part of the package base and the glass cover, and wherein the sealing material layer is formed at a position distant from an inner peripheral end edge of the top of the frame part and distant from an outer peripheral end edge of the top of the frame part.

Abstract: An aluminum nitride sintered compact containing aluminum nitride crystal grains and composite oxide crystal grains containing a rare earth element and an aluminum element, wherein a median diameter of the aluminum nitride crystal grains is 2 ?m or less; 10 to 200 intergrain voids having a longest diameter of 0.2 to 1 ?m are dispersed in a region of a cross section of 100 ?m in square; and the carbon atom content is less than 0.10% by mass. Also disclosed is a method of producing the aluminum nitride sintered compact.

Abstract: A sensor sheet is manufactured by forming a conductive heat-sensitive material 5 over first wiring electrodes 3a and forming second wiring electrodes 4a over the conductive heat-sensitive material 5. For this reason, no adhesion surface (boundary surface), which is formed when adhesion is performed later, exists between the first wiring electrode 3a and the conductive heat-sensitive material 5 and between the conductive heat-sensitive material 5 and the second wiring electrodes 4a.

Abstract: Embodiments of the present disclosure provide an electrostatic chuck for maintaining a flatness of a substrate being processed in a plasma reactor at high temperatures. In one embodiment, the electrostatic chuck comprises a chuck body coupled to a support stem, the chuck body having a substrate supporting surface, and the chuck body has a volume resistivity value of about 1×107 ohm-cm to about 1×1015 ohm-cm in a temperature of about 250° C. to about 700° C., and an electrode embedded in the body, the electrode is coupled to a power supply. In one example, the chuck body is composed of an aluminum nitride material which has been observed to be able to optimize chucking performance around 600° C. or above during a deposition or etch process, or any other process that employ both high operating temperature and substrate clamping features.

Abstract: An electronic device capable of supplying a large current to a circuit pattern containing conductive nanoparticles includes a substrate, a region provided on the substrate, configured to mount an electronic component therein, a first circuit pattern placed within the region and electrically connected to the electronic component, a second circuit pattern connected to the first circuit pattern and configured to supply current to the first circuit pattern from outside of the region. At least a part of the first circuit pattern includes a layer obtained by sintering conductive nanosized particles with a diameter of less than 1 ?m. The second circuit pattern is thicker than the first circuit pattern.

Abstract: A method for predicting the location of mark is performed for a substrate which includes a plurality of electronic device regions each electronic region includes a mark and a reference indication on a first surface and a sawing indication on a second surface opposite to the first surface. The method includes obtaining first and second image information for the first and second surfaces, extracting a sawing line based on the sawing indication in the second image information, calculating a first spaced distance between the sawing line and the reference indication in the first information, calculating a second spaced distance between the sawing line and the reference indication, and predicting the location of the mark based on whether the first and second spaced distances correspond to a predetermined reference distance. The mark is on each of the electronic device regions separated from each other along the sawing line.

Abstract: The present invention provides a glass composition that allows holes with a circular contour and a smooth inner wall to be formed by a collective micro-hole-forming process using a combination of modified portion formation by ultraviolet laser irradiation and etching, the glass composition being adapted for practical continuous production. The present invention relates to a glass for laser processing, the glass having a glass composition including, in mol %: 45.0%?SiO2?70.0%; 2.0%?B2O3?20.0%; 3.0%?Al2O3?20.0%; 0.1%?CuO?2.0%; 0%?TiO2?15.0%; and 0%?ZnO?9.0%, wherein a relationship of 0?Li2O+Na2O+K2O<2.0% is satisfied.

Abstract: In one implementation, a semiconductor package includes an integrated circuit (IC) flip chip mounted on a first patterned conductive carrier, a second patterned conductive carrier situated over the IC, and a magnetic material situated over the second patterned conductive carrier. The semiconductor package also includes a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.

Abstract: A heat-dissipating structure is formed by bonding a first member and a second member, each being any of a metal, ceramic, and semiconductor, via a die bonding member; or a semiconductor module formed by bonding a semiconductor chip, a metal wire, a ceramic insulating substrate, and a heat-dissipating base substrate including metal, with a die bonding member interposed between each. At least one of the die bonding members includes a lead-free low-melting-point glass composition and metal particles. The lead-free low-melting-point glass composition accounts for 78 mol % or more in terms of the total of the oxides V2O5, TeO2, and Ag2O serving as main ingredients. The content of each of TeO2 and Ag2O is 1 to 2 times the content of V2O5, and at least one of BaO, WO3, and P2O5 is included as accessory ingredients, and at least one of Y2O3, La2O3, and Al2O3 is included as additional ingredients.

Abstract: A method for manufacturing an all-solid battery that includes preparing a first green sheet as a green sheet for at least any one of a positive electrode layer and a negative electrode layer and a second green sheet as a green sheet for a solid electrolyte layer, stacking the first green sheet and the second green sheet to form a stacked body, and firing the stacked body with a setter placed in contact with at least one surface of the stacked body. The setter in contact with the at least one surface of the stacked body is 0.11 ?mRa or more and 50.13 ?mRa or less in surface roughness.

Abstract: A crystal unit includes: a capacitor in which a plurality of dielectrics and a plurality of internal electrodes are alternately stacked; a crystal piece arranged above the capacitor and having excitation electrodes on both surfaces thereof; an external electrode formed on a surface of the capacitor; and a first conductor portion formed within the capacitor, and including one end electrically coupled to a first internal electrode among the plurality of internal electrodes, the other end electrically coupled to the external electrode, and a first exposed portion exposed on the surface of the capacitor between the one end and the other end.

Abstract: [Problem] The aim of the present invention lies in providing a glass ceramic sintered compact in which dielectric loss in a high-frequency region is reduced, without any reduction in sintering density, and also in providing a wiring board employing same. [Solution] A glass ceramic sintered compact containing a glass component, a ceramic filler and a composite oxide, characterized in that the glass component is crystallized glass on which is deposited a diopside oxide crystal phase including at least Mg, Ca and Si, and the composite oxide includes at least Al and Co.

Abstract: Chemical methods, optionally in combination with physical methods, may be used to increase the strength of the bond formed by a braze material between a polycrystalline material and a hard composite. Such polycrystalline materials brazed to hard composites may be found in various wellbore tools include drill bit cutters. An exemplary method may include forming a bonding layer on a bonding surface of a polycrystalline material body that comprises a hard material, the bonding surface opposing a contact surface of the polycrystalline material body, and the bonding layer substantially formed by a [111] crystal structure of the hard material, a [100] crystal structure of the hard material, or a combination thereof; and brazing the bonding layer to a hard composite using a braze material.

Abstract: A method of forming a connection receptacle over a substrate includes printing a first dielectric layer over the substrate between first and second transmission lines, the first dielectric layer having a tapered cross-section along a plane extending from the first transmission line to the second transmission line; disposing a conductive layer over the printed first dielectric layer; and electrically connecting the conductive layer to a conductor of the first transmission line and a conductor of the second transmission line.

Abstract: A storage element for a solid electrolyte battery is provided, having a main member of a porous ceramic matrix in which particles, that are made of a metal and/or a metal oxide and jointly form a redox couple, are embedded, the particles having a lamellar shape.

Abstract: A method for processing a powder material includes cleaning surfaces of a powder material that has spherical metal particles, coating the cleaned surfaces with an organic bonding agent, mixing the coated particles with a dispersion that contains ceramic nanoparticles, drying the mixture to remove a carrier of the dispersion and deposit the ceramic nanoparticles with a spaced-apart distribution onto the organic bonding agent on the surfaces of the particles, and thermally removing the organic bonding agent to attach the ceramic nanoparticles to the surface of the particles.

Abstract: Provided are: a circuit device which has improved connection reliability in a solder joint portion by suppressing the occurrence of sink of solder; and a method for manufacturing the circuit device. In a method for manufacturing a circuit device of the present invention, a plurality of solders (19), which are apart from each other, are firstly formed on the upper surface of a pad (18A), and a chip component (14B) and a transistor (14C) are affixed at the same time. After that, a solder paste (31) is supplied to the upper surface of the pad (18A) using a syringe (30), a heatsink (14D) is mounted on top of the solder paste (31), and melting is caused by a reflow process. There is little risk of sinking of the solders (19) in the present invention since the solders (19) are discretely arranged on the upper surface of the pad (18A).

Abstract: Disclosed is a solid oxide fuel cell which includes an inner electrode, a solid electrolyte, and an outer electrode, each being sequentially laminated on the surface of a porous support. The porous support contains forsterite, and further has a strontium element concentration of 0.02 mass % to 1 mass % both inclusive in terms of SrO based on the mass of the forsterite.

Abstract: In one embodiment, a processing chamber is disclosed wherein at least one surface of the processing chamber has a coating comprising SivYwMgxAlyOz, wherein v ranges from about 0.0196 to 0.2951, w ranges from about 0.0131 to 0.1569, x ranges from about 0.0164 to 0.0784, y ranges from about 0.0197 to 0.1569, z ranges from about 0.5882 to 0.6557, and v+w+x+y+z=1.

Abstract: An insulating layer forming material and an insulating layer forming paste capable of forming an insulating layer on a metallic substrate without the filler and glass reacting or warpage occurring even when repeatedly fired at 850° C. or higher are provided. The insulating layer forming material containing a lead-free glass composition and an ?-quartz filler contains 17.0-40.0 wt. % of the ?-quartz filler and 60.0-83.0 wt. % of the lead-free glass composition. The ?-quartz filler has an average particle diameter (D50) of 1.0-3.5 ?m and a specific surface area of 2.5-6.5 m2/g. The lead-free glass composition includes no B2O3 and comprises a composition, in mol %, of 40.0-60.0% SiO2, 0.5-10.0% Al2O3, 20.0-45.0% MgO+CaO+SrO+BaO, 5.0-23.0% ZnO, and 0-10.0% Li2O+Na2O+K2O.

Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Abstract: A wiring substrate includes a substrate body formed of a plate-like ceramic, having a front surface, a back surface, and a height of 0.8 mm or less; a cavity opening at the front surface and having a rectangular shape as viewed in plane; and side walls having a thickness of 0.3 mm or less between a side surface of the cavity and a side surface of the substrate body. The wiring substrate further includes an electrically conductive layer having the form of a frame and formed on the front surface to surround an opening of the cavity; a ceramic surface having the form of a frame and located adjacently to the electrically conductive layer and along the outer periphery of the front surface; and a via conductor formed in the substrate body along the side surface of the cavity between a bottom surface of the cavity and the front surface.

Abstract: When a multilayer ceramic substrate with a cavity is reduced in thickness, a bottom wall portion defining the bottom of the cavity is reduced in thickness, thereby leading to the problem that the bottom wall portion is likely to be broken. A bottom wall portion defining a cavity of a multilayer ceramic substrate has a stack structure formed with a high thermal expansion coefficient layer sandwiched between first and second low thermal expansion coefficient layers. This configuration generates compression stress in the low thermal expansion coefficient layers during a cooling process after firing, thereby allowing the mechanical strength at the bottom wall portion to be improved.

Abstract: A semiconductor arrangement includes a ceramic mount and at least one semiconductor component fixed-to the ceramic mount. The ceramic mount includes a first section, and the first section is electrically conductive.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: An electric device with an insulating substrate consisting of an insulating layer and at least one metallization on a surface side of the insulating layer, the metallization being structured and having an electric component on the metallization. The metallization has a layer thickness that is stepped and is greater in an area adjoining the component.

Abstract: A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.

Abstract: An assembly includes an integrated circuit die coupled to another component of the assembly with an alkali silicate glass material. The alkali silicate material may include particles for modifying the thermal, mechanical, and/or electrical characteristics of the material.

Abstract: The semiconductor device 1 includes a substrate 3, a semiconductor chip 4 mounted on the substrate 3, the substrate 3, a bump 5 connecting the substrate 3 and the semiconductor chip 4, and an underfill 6 filling in around the bump 5. In the case of a bump 5 composed of a high-melting-point solder having a melting point of 230° C. or more, the underfill 6 is composed of a resin material having an elastic modulus in the range of 30 MPa to 3000 MPa. In the case of a bump 5 composed of a lead-free solder, the underfill 6 is composed of a resin material having an elastic modulus in the range of 150 MPa to 800 MPa. An insulating layer 311 of buildup layers 31 of the substrate 3 has a linear expansion coefficient of 35 ppm/° C. or less in the in-plane direction of the substrate at temperatures in the range of 25° C. to the glass transition temperature.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: A chip package comprising a glass substrate, wherein a first opening in the glass substrate passes vertically through the glass substrate, a semiconductor chip, a wiring structure comprising a first portion in the first opening and a second portion over the glass substrate, wherein the first portion is connected to the semiconductor chip, wherein the wiring structure comprises a passive device, wherein the wiring structure comprises copper, and a dielectric layer over the glass substrate and on the wiring structure, wherein a second opening in the dielectric layer is over a contact point of the wiring structure, and the contact point is at a bottom of the second opening.

Abstract: A semiconductor device includes a substrate including a first metal layer, a first semiconductor chip having sidewalls, and a first solder layer contacting the first semiconductor chip and the first metal layer. The first metal layer includes a groove extending around sidewalls of the first semiconductor chip. The groove is at least partly filled with excess solder from the first solder layer.

Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.

Abstract: This disclosure provides systems, methods and apparatus for glass packaging of integrated circuit (IC) and electromechanical systems (EMS) devices. In one aspect, fabricating a glass package includes joining a cover glass panel to a glass substrate panel, and singulating the joined panels to form individual glass packages, each including one or more encapsulated devices and one or more signal transmission pathways. In another aspect, a glass package may include a glass substrate, a cover glass and one or more devices encapsulated between the glass substrate and the cover glass.

Abstract: A power block includes an insulating substrate, a conductive pattern formed on the insulating substrate, a power semiconductor chip bonded onto the conductive pattern by lead-free solder, a plurality of electrodes electrically connected to the power semiconductor chip and extending upwardly away from the insulating substrate, and a transfer molding resin covering the conductive pattern, the lead-free solder, the power semiconductor chip, and the plurality of electrodes, wherein surfaces of the plurality of electrodes are exposed at an outer surface of the transfer molding resin and lie in the same plane as the outer surface, the outer surface being located directly above the conductive pattern.

Abstract: A method for producing a capping wafer for a sensor having at least one cap includes: production of a contacting via extending through the wafer, and, temporally subsequent thereto, filling of the contacting via with an electrically conductive material.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.