Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: In a method and system for fabricating a semiconductor device (100) having a package-on-package structure, a base laminate substrate (BLS) (110) is formed to include a base center portion (112) and a peripheral portion (114) separated by a barrier element (120). The barrier element (120) forms a peripheral wall (118) to surround the base center portion (112). A frame shaped top laminate substrate (TLS) (130) is disposed over the peripheral portion (114) of the BLS (110). The TLS (130) has an open top center portion (132) matching the base center portion (112) surrounded by the peripheral wall (118) to form a cavity (140). A plurality of conductive bumps (150) each disposed between a top contact pad (134) of the TLS and a base contact pad (116) of the peripheral portion (114) of the BLS (110) are formed to provide electrical and mechanical coupling therebetween. The barrier element (120) forms a seal between the cavity (140) and the plurality of conductive bumps (150).

Abstract: An apparatus including a first electrode; a second electrode; a first and second ceramic material disposed between the first electrode and the second electrode, the second ceramic material having a greater electrical conductivity than the first ceramic material. A method including forming a first ceramic material film and a different second ceramic material film on a first electrode; and forming a second electrode on the second ceramic material film to form a capacitor structure having the first ceramic material film and the second ceramic material film disposed between the first electrode and the second electrode, wherein the first ceramic material has a conductivity selected to dampen undesired oscillations in electrical device operation to which the capacitor structure may be exposed. An apparatus including a first electrode; a second electrode; and a composite dielectric including a plurality of dielectric films including a different Curie temperature.

Abstract: An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.

Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.

Abstract: The present invention provides a structure of memory card comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through hole structure formed there through, traces formed within the substrate; a first die disposed within the die receiving cavity; a first dielectric layer formed on the first die and the substrate; a first re-distribution layer (RDL) formed on the first dielectric layer, wherein the first RDL is coupled to the first die and the traces; a second dielectric layer formed over the first RDL; a second die disposed on the second dielectric layer; a third dielectric layer formed over the second dielectric layer and the second die; a second RDL formed on the third dielectric layer, wherein the second RDL is coupled to the second die and the first RDL; a forth dielectric layer formed over the second RDL; a third die formed over the forth dielectric layer and coupled to the second RDL; a fifth dielectric layer formed around the third die; and a plastic c

Abstract: A semiconductor device comprises a semiconductor element and a support body made of a stack of ceramic layers having a recess in which electrical conductors are electrically connected with the semiconductor element, wherein at least a part of a top face of a recess side wall is covered by a resin, thereby providing a light emitting device.

Abstract: A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (?m).

Abstract: An adhesive tape having an adhesive layer formed on one side of a substrate layer, which renders it possible to minimize the extent of development of chipping or fragmentation (nicks) or crack in chip when the silicon wafer, to which this tape is adhered, is cut into chips using a dicer. The adhesive layer of the tape has a storage modulus G? of 1 MPa or more at a temperature of 15 to 35° C., and preferably tan ? as represented by the ratio of a loss modulus G? to the storage modulus G? is 0.05 or less. The adhesive layer is preferably constructed principally of an olefin polymer.

Abstract: [PROBLEM ] To provide a laminate ceramic electronic device applicable to two types of design specifications by using a common package. [SOLUTION A laminate ceramic electronic device of the present invention has filter chips 2, 3 for transmission and reception mounted therein. A wiring pattern 7, which connects an input terminal A of the transmission filter chip 2 with a transmission side signal terminal Tx in a first arrangement, has two branch wiring portions 72, 73 extending from the transmission side signal terminal Tx toward the input terminal A of the transmission filter chip 2 in the first arrangement and toward an output terminal D of the reception filter chip 3 in a second arrangement.

Abstract: A press mold for fabricating a glass substrate, the glass substrate comprising a substrate; and a terrace-shaped flat portion formed on the substrate and having a grooved portion formed therein, is characterized in that the press mold comprises a top mold and a bottom mold; at least one of the top mold and the bottom mold having an indented portion formed therein so as to correspond to the terrace-shaped flat portion, the indented portion having an entire periphery surrounded by a mold reference surface.

Abstract: A power amplifier module (IC module) of stacked layer structure is miniaturized while dissipating heat from a power amplifier chip. The module includes a first LTCC wiring board having a cavity in which a power amplifier chip is embedded, and a plurality of vias, which are electrically connected to ground, immediately underlying the power amplifier chip; and a second LTCC wiring board joined to the first LTCC wiring board and incorporating a matching circuit and a bias circuit electrically connected to the power amplifier chip. Ground pads of the matching circuit and bias circuit are all grounded by separating wiring or vias in the first LTCC wiring board and second LTCC wiring board.

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

Abstract: There is provided an aluminum/ceramic bonding substrate having a high reliability to high-temperature heat cycles. An aluminum member of an aluminum alloy having a Vickers hardness of 35 to 45 is bonded to a ceramic substrate having a flexural strength of 500 to 600 MPa in three-point bending. The ceramic substrate is made of high-strength aluminum nitride, silicon nitride, alumina containing zirconia, or high-purity alumina. The aluminum alloy is an aluminum alloy containing silicon and boron, or an aluminum alloy containing copper.

Abstract: A wafer dicing process for optical electronic packing is provided. The process includes: providing a first wafer (glass wafer) and a second wafer (interposer wafer); etching the second wafer to form a reference flat coordinate; laminating the first wafer on the second wafer; providing a third wafer (CMOS wafer); laminating the third wafer under the second wafer; cutting the first wafer by a first dicing saw according to the reference flat coordinate; and cutting the third wafer by a second dicing saw to form a first reference axis and a second reference axis perpendicular to each other and to establish a backside dicing reference coordinate. The process not only can reduce wearing loss of the dicing saws but also ensure to form high quality cutting edges and a precise backside dicing reference coordinate.

Abstract: A multilayer circuit carrier, electronic devices and panel, and a method for producing a multilayer circuit carrier include at least one semiconductor chip, at least one rewiring layer with a rewiring structure, and at least one insulation layer, which has passage structures.

Abstract: A wafer scale semiconductor integrated circuit packaging technique provides a hermetic seal for the individual integrated circuit die formed as part of the wafer scale structure. A semiconductor wafer is manufactured to include a number of individual semiconductor die. Each individual die formed on the wafer includes a number of bond pads that are exposed on the die surface in various locations to provide electrical connections to the circuitry created on the die. The wafer further includes a planar glass sheet that is substantially the same size as the wafer, the glass sheet being adhered to the wafer using a suitable adhesive. The glass sheet has a number of pre-formed holes in it, the arrangement of the pre-formed holes corresponding to the location of the bond pads at each of the individual semiconductor die formed as part of the wafer structure.

Abstract: A microelectromechanical device package and a low-stress inducing method for packaging a microelectromechanical device are disclosed in this invention. The microelectromechanical device is accommodated within a cavity comprised by a first package substrate and a second substrate, wherein a third substrate is disposed between and bonded to both the microelectromechanical device lower semiconductor substrate and the package bottom substrate. The first and second package substrates are then bonded so as to package the microelectromechanical device inside.

Abstract: A composite laminate, including shrink-prevention ceramic green sheets arranged on the main surfaces of an unfired ceramic laminate and having a sintering temperature greater than the firing temperature of the unfired ceramic laminate, is fired at a temperature which is greater than the sintering temperature of the unfired ceramic laminate, and which is less than the sintering temperature of the shrink-prevention ceramic green sheet. Thereafter, the shrink-prevention ceramic green sheets are removed in a first removing step of spraying water and compressed gas against the shrink-prevention ceramic green sheets so as to remove a portion thereof that has not reacted with a glass component of the unfired ceramic laminate, and in a second removing step of ceramic powder, spraying water, and compressed air, such that a residual material not removed in the first removing step is removed, and in a third removing step of supersonic-cleaning the ceramic multi-layer substrate after the first and second steps.

Abstract: An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor's performance and may provide better structural support.

Abstract: An electronic assembly comprising one or more high performance integrated circuits includes at least one high capacity heat sink. The heat sink, which comprises a number of fins projecting substantially radially from a core, is structured to capture air from a fan and to direct the air to optimize heat transfer from the heat sink. The heat sink fins can be formed in different shapes. In one embodiment, the fins are curved. In another embodiment, the fins are bent. In yet another embodiment, the fins are curved and bent. Methods of fabricating heat sinks and electronic assemblies, as well as application of the heat sink to an electronic assembly and to an electronic system, are also described.