Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.

Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface.

Abstract: A Micro-Electro-Mechanical Systems (MEMS) device includes a first substrate with a first surface and a second surface, the first substrate including a base layer, a moveable beam disposed on the base layer, at least one metal layer, and one or more standoffs disposed on the base layer such that one or more metal layers are situated on the top surface of the one or more standoffs. The MEMS device further includes a second substrate including one or more metal layers bonded to the one or more standoffs resulting in an electrical connection between at least a portion of the one or more metal layers of the second substrate and one or more of the at least one electrode on the bottom surface and the at least one electrode on the top surface.

Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located atop a substrate. The inorganic antireflective coating comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. The at least one cured and patterned low-k dielectric material and the patterned inorganic antireflective coating have conductively filled regions embedded therein and the at least one cured and patterned low-k dielectric material has at least one airgap located adjacent, but not directly in contact with the conductively filled regions.

Abstract: A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer.

Abstract: Provided by some aspects of the invention is a relatively low-cost, relatively highly accurate physical quantity sensor, and a manufacturing method thereof, that relaxes thermal stress from an outer peripheral portion of a diaphragm in a silicon-on-nothing (“SON”) structure. By providing a stress relaxation region (trench groove) in an outer peripheral portion of a diaphragm in a SON structure, there can be, in some aspects of the invention, a benefit of relaxing the transmission to the diaphragm of thermal stress generated by the difference in linear expansion coefficient between a package and chip, and it is possible to relax the transmission to an electronic circuit disposed in an outer peripheral portion of mechanical stress generated by a measured pressure. As a result of this, it is possible to provide a highly accurate physical quantity sensor.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.

Abstract: A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.

Abstract: A method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material is provided. Specifically, a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating is provided.

Abstract: Reliable electrical contact is made with electronic components and effective electrical isolation is produced between the top and bottom of the electronic components. An electronic component is arranged inside a window in a first layer on a substrate. Next, a second layer is put on such that contact areas on the component and contact points on the first layer are freely accessible. Electrical contacts and electrical connecting lines are produced by electrodeposition. The second layer is used to produce bridges over an interval range between the electronic component and the first layer. The bridges have connecting lines formed on them. The second layer can be removed again. Radio-frequency modules can be produced in compact fashion and can be combined with audio-frequency components.

Abstract: To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.

Abstract: A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.

Abstract: A method for manufacturing a semiconductor photodetector includes: forming an insulating film on a semiconductor substrate; forming an electrode on and in contact with a predetermined area of a surface of the semiconductor substrate; forming a resist on the insulating film after forming the electrode; forming a power supply layer of a metal on the resist and the electrode; plating a surface of a portion of the power supply layer with a metal coating, after forming the power supply layer, the portion overlying and being in contact with the electrode; after the plating, etching and removing a part of the power supply layer leaving a portion that is covered with the metal coating and is an extension of the electrode; and removing the resist after etching the power supply layer.

Abstract: A semiconductor die is described. This semiconductor die includes an electro-static discharge (ESD) device with a metal component coupled to an input-output (I/O) pad, and coupled to a ground voltage via a signal line. Moreover, adjacent edges of the metal component and the I/O pad are separated by a spacing that defines an ESD gap. When a field-emission or ionization current flows across the ESD gap, the metal component provides a discharge path to the ground voltage for transient ESD signals. Furthermore, the ESD gap is at least partially enclosed so that there is gas in the ESD gap.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the liner, which is subsequently removed to form an air gap around the conductive material of the through-silicon via. A dielectric layer is formed of the backside of the semiconductor substrate to seal the air gap.

Abstract: To provide a semiconductor device prevented from giving a limitation on the sensitivity of HEMS devices due to isolation regions thereof and a method of fabricating the same.

Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removale of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; an electrode in a device region on the main surface; a metal wiring on the main surface and having a first end connected to the electrode; an electrode pad outside the device region and spaced from the metal wiring; an air gap between the main surface and an air gap forming film on the main surface, enveloping the first end of the metal wiring and the electrode, and having a first opening; a resin closing the first opening and covering a second end of the metal wiring; a liquid repellent film facing the air gap and increasing contact angle of the resin, when liquid, relative to contact angles on the semiconductor substrate and the air gap forming film; and a metal film connecting the metal wiring to the electrode pad through a second opening located in the resin.

Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Abstract: An integrated circuit structure includes a triple-axis accelerometer, which further includes a proof-mass formed of a semiconductor material; a first spring formed of the semiconductor material and connected to the proof-mass, wherein the first spring is configured to allow the proof-mass to move in a first direction in a plane; and a second spring formed of the semiconductor material and connected to the proof-mass. The second spring is configured to allow the proof-mass to move in a second direction in the plane and perpendicular to the first direction. The triple-axis accelerometer further includes a conductive capacitor plate including a portion directly over, and spaced apart from, the proof-mass, wherein the conductive capacitor plate and the proof-mass form a capacitor; an anchor electrode contacting a semiconductor region; and a transition region connecting the anchor electrode and the conductive capacitor plate, wherein the transition region is slanted.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.

Abstract: To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor chips, and a first sealing material. The substrate may include, but is not limited to, a chip mounting area and a higher-level portion. The higher level portion surrounds the chip mounting area. The higher-level portion is higher in level than the chip mounting area. The stack of semiconductor chips is disposed over the chip mounting area. A first sealing material seals the stack of semiconductor chips. The first sealing material is confined by the higher-level portion.

Abstract: An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles, which may be formed in a surface of the substrate and expose contacts of the second set, may be configured to at least partially receive conductive structures that are secured to the contact pads of the second set. Thus, the interposer may be useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages.

Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

Abstract: A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.

Abstract: A semiconductor device includes a substrate, a die assembly attachable to the substrate and a flexible strip extending over the substrate and the die assembly. The flexible strip has one or more routing circuits carried thereon. The die assembly and the substrate are arranged to be electrically connected through the one or more routing circuits carried on the flexible strip.

Abstract: Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

Abstract: A mother thin film transistor (TFT) array substrate includes an insulating substrate, at least two TFT arrays and printed wirings. The TFT array includes TFTs formed on the insulating substrate. The printed wirings are connected to the TFT arrays. The printed wiring includes a discontinuous metal layer and at least one bridge layer connecting the discontinuous metal layer. The bridge layer is made from corrosion-resistant material.

Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Abstract: A semiconductor device has a substrate. A first die is electrically attached to a first surface of the substrate. A shield spacer having a first and second surface is provided wherein the second surface of the shield spacer is attached to a first surface of the first die. A plurality of wirebonds are attached to the shield spacer and to the substrate. A mold compound is provided for encapsulating the first die, the shield spacer, and the wirebonds.

Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.

Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.

Abstract: A package (216) for electrically connecting an integrated circuit (212) to a printed circuit board (214) includes a mount array (219) and a substrate body (216A). The mount array (219) is electrically connected to the integrated circuit (212). The mount array (219) includes a plurality of positive terminal mounts (342), a plurality of negative terminal mounts (344), and a plurality of signal mounts (346). The substrate body (216A) includes a first conductive layer (220a), a second conductive layer (220b), and an insulating layer (222a) that is positioned between the first conductive layer (220a) and the second conductive layer (220b). The first conductive layer (220a) includes (i) a terminal portion (350) that is connected one of the terminal mounts (342) (344), and (ii) a signal portion (352) that is connected to the signal mounts (346). Further, the second conductive layer (220b) is directly connected to the other of the terminal mounts (344) (342).

Abstract: A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending away from the die attach pad in at least two directions. An inventive lead frame features “up-set” bonding pads electrically connected with the die attach pad and arranged with a bonding surface for supporting a plurality of wire bonds. The bonding surfaces also constructed to define at least one mold flow aperture for each up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.

Abstract: A module, which in one embodiment may be a packaged millimeter waver module, includes a semiconductor lid portion; a packaging portion attached to the lid portion, wherein the packaging portion comprises a plurality of vias, a carrier portion, wherein a first semiconductor die is attached to the carrier portion, the packaging portion is attached to the carrier portion so that the packaging portion is over the carrier portion and the semiconductor die is within an opening in the packaging portion, and the lid portion and the carrier portion form an first air gap around the first semiconductor device.

Abstract: One aspect of the invention relates to a power semiconductor device in lead frame technology and a method for producing the same. The power semiconductor device has a vertical current path through a power semiconductor chip. The power semiconductor chip has at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a lead frame chip island of a lead frame and the top side electrode is electrically connected to an internal lead of the lead frame via a connecting element. The connecting element has an electrically conductive film on a surface facing the top side electrode, the electrically conductive film extending from the top side electrode to the internal lead.

Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips.

Abstract: A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.

Abstract: An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer.

Abstract: An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles, which may be formed in a surface of the substrate and expose contacts of the second set, may be configured to at least partially receive conductive structures that are secured to the contact pads of the second set. Thus, the interposer may be useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages.

Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metallized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metallized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

Abstract: A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.