Abstract: A semiconductor device includes a semiconductor substrate including an active element or an integrated circuit and a plurality of connection electrodes to be electrically connected to the integrated circuit; a first resin layer formed on a surface of the semiconductor substrate on which the connection electrodes are formed in such a manner avoiding the connection electrodes; a connection wiring layer formed between the semiconductor substrate and the first resin layer and connected to one of the plurality of connection electrodes; a Cu wiring layer connected at one end thereof to the connection wiring layer and formed on the surface of the first resin layer; a passive element composed of the connection wiring layer and the Cu wiring layer; a second resin layer for covering a surface of the Cu wiring layer; and an external terminal electrically connected to some of the plurality of connection electrodes and formed such that a portion of the second resin layer protrudes from the second resin layer.

Abstract: A semiconductor device without cantilevered leads uses conductive wires (120) to connect the chip terminals to the leads (110), and a package compound (140) to encapsulate the chip surface (101a) with the terminals, the wires, and the lead surfaces with the attached wires. The chip surface (101b) opposite the terminals together with portions (103) of the chip sidewalls protrude from the package, allowing an unimpeded thermal contact of the protruding chip surface to a substrate (201) to optimize the thermal flux from the chip to the substrate. Solder bodies (250) attached to the compound-free lead surfaces (113b) can be connected to the substrate so that the solder bodies are as elongated as the protruding chip height, facilitating the void-free distribution of an underfill compound into the space between chip and substrate, and improving the absorption of thermomechanical stresses during device operation.

Abstract: A wiring board is provided with an external connection terminal to which an electrode terminal of an electronic component is to be connected. The external connection terminal is formed so that a portion thereof is electrically connected to a pad portion exposed from an outermost insulating layer on an electronic component mounting surface of a wiring board body and so that an air gap is kept between a portion of the external connection terminal, to which the electrode terminal of the electronic component is to be connected, and the insulating layer.

Abstract: A mountable integrated circuit package system includes: providing a substrate having an opening provided therein; providing an encapsulated integrated circuit package having an external leadfinger; mounting the encapsulated integrated circuit package by the external leadfinger proximate to the opening in the substrate; and connecting the external leadfinger and the substrate.

Abstract: A semiconductor module preferably includes a semiconductor package and a printed circuit board (PCB). The semiconductor package can include an outer terminal. The PCB can include a terminal land that is electrically connected to the outer terminal. The PCB preferably has a recess configured to at least partially expose the terminal land and to receive the outer terminal. The recess preferably has a width that is less than a width of the semiconductor package. Damage to edge portions of the semiconductor package whose outer terminal is received into the recess may be prevented, because the edge portions make contact with and are supported by the PCB. One or more support members can also be provided to contact one or more sides of the edge portions of the semiconductor package to further prevent damage due to horizontal impacts.

Abstract: A semiconductor device (601) is provided which comprises a substrate (603); a semiconductor device (605) disposed on said substrate and having a first major surface; a first metal strap (615) which is in electrical contact with said substrate and which is adapted to provide power to a first region (608) of said semiconductor device; and a second metal strap (616) which is in electrical contact with said substrate and which is adapted to provide ground to a second region (609) of said semiconductor device.

Abstract: Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap.

Abstract: A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device.

Abstract: A cavity or die down ball grid array package includes an interposer substrate structure attached to the die. In an example, the interposer substrate reduces the interconnect length from a board to which the package mounts to power and ground pads on a top layer of the semiconductor or integrated circuit (IC) die. In this example, the interposer substrate also removes the requirement that power and ground pads be located on a periphery of the die. Power and ground pads can be located in an interior region on a top metal layer where they can be interconnected to the interposer substrate using electrically conductive bumps or wire bond(s).

Abstract: A transistor is located on a GaAs substrate. An air bridge extends to provide a cavity above gate electrodes of the transistor. An opening is sealed by the end ball of a second wire. Further, the semiconductor device is wholly covered by sealing resin.

Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

Abstract: In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.

Abstract: In some embodiments, an apparatus and a system are provided. The apparatus and the system may comprise a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site. The first surface activated bonding site may comprise a first clean metal and the second surface activated bonding site may comprise a second clean metal. If the first surface activated bonding site is coupled to the second surface activated bonding site respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: A method of forming a dielectric layer is provided. A first dielectric layer is formed on a substrate having metal layers formed thereon. The first dielectric layer includes overhangs in the spaces between two neighboring metal layers and voids under the overhangs. The first dielectric layer is partially removed to cut off the overhangs and expose the voids and therefore openings are formed. A second dielectric layer is formed on the dielectric layer to fill up the opening.

Abstract: A digital camera module (100) includes a chip package (110) and a lens module (130), mounted on the chip package, for forming a focused image on the chip package. The chip package includes a supporter (112), a chip (114), a plurality of wires (116), a main adhesive (118), and a cover plate (119). The supporter includes a through hole defined therethrough and has a plurality of top contacts (1130) formed thereon around the through hole. The chip is disposed in the through hole and includes a plurality of pads (1144) arranged thereon. The wires electrically connect the pads to the top contacts. The main adhesive is applied to a gap between the chip and the supporter and fixes the chip to the supporter. The cover plate is adhered and supported on the main adhesive. A method for making the chip package is also provided.

Abstract: Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Abstract: In one embodiment, a reflowable layer 51 is deposited over a semiconductor device 10 and reflowed in an environment having a pressure approximately equal to that of atmosphere to form a seal layer 52. The seal layer 52 seals all openings 43 in the underlying layer of the semiconductor device 10. Since the reflow is performed at approximately atmospheric pressure a gap 50 which was coupled to the opening 43 is sealed at approximately atmospheric pressure, which is desirable for the semiconductor device 10 to avoid oscillation. The seal layer 52 is also desirable because it prevents particles from entering the gap 50. In another embodiment, the seal layer 52 is deposited in an environment having a pressure approximately equal to atmospheric pressure to seal the hole 43 without a reflow being performed.

Abstract: A semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. A solder bump is formed on the contact pad. An electrostatic discharge (ESD) bump electrode is formed on the contact pad. The ESD bump electrode has a tip. The ESD bump electrode is made with gold. A chip carrier substrate has a contact pad metallurgically connected to the solder bump. The chip carrier substrate also has a ground plate. The ground plate is a low impedance ground point. The tip of the ESD bump electrode is separated from the ground plate by a distance according to ESD sensitivity of the active devices. The distance is determined by a ratio of a discharging threshold voltage for ESD sensitivity of the active device to be protected to an atmosphere discharging voltage.

Abstract: Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

Abstract: A first semiconductor chip includes a fixed electrode formed on a first semiconductor substrate and a plurality of first metal spacers formed on a first interlayer dielectric. A second semiconductor chip includes a vibrating electrode formed on a second semiconductor substrate and a plurality of second metal spacers formed on a second interlayer dielectric. The first and second semiconductor chips are metallically bonded to each other using the first and second metal spacers. An air gap is formed in a region of the condenser microphone located between the first semiconductor chip and the second semiconductor chip except bonded regions of the first and second metal spacers.

Abstract: One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip.

Abstract: A component having an airdome enclosure that protects the component from its external environment. An airdome enclosure according to the present techniques avoids the high costs of employing special materials and/or specialized process steps in the manufacture of a component. An electronic component according to the present techniques includes a set of substructures formed on a substrate and an airdome enclosure over the substructures that protects the substructures and that hinders the formation of parasitic capacitances among the substructures.

Abstract: Provided is a semiconductor and a method for forming the same. The method includes forming a buried insulating layer locally in a substrate. The substrate is etched to form an opening exposing the buried insulating layer, and a silicon pattern spaced in at least one direction from the substrate is formed on the buried insulating layer. A first insulating layer is formed to enclose the silicon pattern.

Abstract: A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Abstract: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.

Abstract: An intermediate semiconductor structure is disclosed. The semiconductor structure includes a substrate; a relaxed Si1-xGex layer on the substrate, the relaxed Si1-xGex layer having at least one trench; an un-etched Si layer portion on the substrate and beneath the relaxed Si1-xGex layer along a periphery of the substrate providing structural support for the relaxed Si1-xGex layer along the periphery of the substrate; and at least one void between the relaxed Si1-xGex layer and the substrate, wherein the void encompasses an entire surface area of the substrate but for a portion of the substrate in contact with the un-etched Si layer portion.

Abstract: A wafer or a portion of a wafer including capped chips such as surface acoustic wave (SAW) chips is provided with terminals by applying a terminal-bearing element such as a dielectric element with terminals and leads thereon, or a lead frame, so that the terminal-bearing element covers the caps, and the leads are aligned with channels or other depressions between the caps. The leads are connected to contacts on the wafer, and the wafer is severed to form individual units, each including terminals supported by the cap and connected to the contacts by the leads. The resulting units can be handled and processed in the same manner as ordinary chips or chip assemblies.

Abstract: The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same. The conductor tracks extend from contact areas on the top side of the semiconductor chip to contact pads on the circuit carrier. The conductor tracks include an electrically conductive polymer in the semiconductor device.

Abstract: The invention relates to a method for manufacturing a structure of electrical interconnections of the damascene type for an integrated circuit, comprising at least one level of interconnections, consisting of electrical conductors arranged on a substrate and separated from one another by air gaps, a layer of electrically isolating material covering the level of interconnections, the method comprising steps consisting of: depositing a layer of sacrificial material on the substrate, etching the layer of sacrificial material with a pattern corresponding to the electrical conductors, depositing, on the etched layer of the layer of sacrificial material, a layer of membrane in material permeable to an attack agent capable of breaking down the sacrificial material, breaking down the sacrificial material by means of the attack agent, which is how the air gaps are formed in place of the broken down sacrificial material, forming electrical conductors in the etched track so as to obtain electrical conductors separate

Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

Abstract: Thinning and stacking are essential for circuit modules used for mobile devices of various kinds, smart cards, memory cards and the like. These demands make the manufacture of the circuit modules more complicated or less reliable due to delamination. A circuit module of a multilayer structure is provided which is formed by embedding semiconductor chips and passive components in a sheet made from a thermoplastic resin; folding a module sheet, which is formed of circuit blocks provided with wiring patterns thereon, at the boundaries of the circuit blocks so as to be stacked into layers; and thermal-bonding and integrating the module sheet by applying heat and pressure. As a result, a highly reliable circuit module can be manufactured in a simple manner.

Abstract: After a HEMT is formed, side walls are formed on a semiconductor substrate. Next, a sacrificial layer is formed to cover the HEMT. Next, contact holes are formed in the sacrificial layer to expose upper surfaces of source electrodes. Next, a metal interconnect line is formed by patterning a metal film formed on the entire top surface. Next, slits are formed in the metal interconnect line to partially expose an upper surface of the sacrificial layer. After the sacrificial layer is dissolved, the dissolved sacrificial layer is discharged through the slits to the outside. An air space is formed as a result of the removal of the sacrificial layer.

Abstract: A field effect transistor structure includes a single crystal substrate having: a source, gate and drain electrodes disposed on an upper surface of the substrate, the gate electrode having a region thereof disposed between a region of the drain electrode and a region of the source electrode; a ground conductor disposed on a lower surface of the substrate; a plurality of electrically conductive vias passing through the substrate, each one of the vias having one end electrically connected to a different region of the ground conductor and having another end electrically connected to the gate electrode. The plurality of electrically conductive vias provide parallel and symmetric connections between the gate electrode and the ground conductor.

Abstract: A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.

Abstract: Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer including an interconnect structure, where the dielectric layer is formed of a dielectric material including Si, C and O. The damascene stack also includes a converted portion of the dielectric layer, where the converted portion is adjacent to the at least one interconnect structure and has a lower carbon content than the dielectric material. The damascene stack also includes an airgap formed adjacent to the interconnect structure, the airgap being formed by removing at least part of the converted portion using an etch compound.

Abstract: A method of forming a floating gate of a flash memory device wherein a hard mask nitride film is stripped using two or more etching steps. Accordingly, a seam can be prevented when depositing a floating gate polysilicon film. Furthermore, the floating gate polysilicon film may be blanket-etched to make rounded upper edge portions of the floating gate polysilicon film. In this way, a void can be prevented when depositing a control gate polysilicon.

Abstract: An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first interface and the second interface, and attaching a third integrated circuit package on the second integrated circuit package.

Abstract: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.

Abstract: A semiconductor package is disclosed. In one embodiment the package includes comprises a semiconductor chip including an active surface with a plurality of chip contact areas and a package substrate including a plurality of first contact areas and a plurality of second contact areas on its bottom surface. The chip is mounted on the package substrate with its active surface facing the package substrate. A plurality of conducting means provide electrical contact between the chip contact areas and the first contact areas. A heat spreading means comprises a planar area and at least one protrusion. The planar area is attached to the upper surface of the chip and the protrusion is attached to the upper surface of the package substrate.

Abstract: The semiconductor device, including an electrode formed on the surface of a semiconductor element; and a metallic ribbon connected to the electrode. The metallic ribbon has a depressed portion on a surface contacting to the electrode, and the metallic ribbon is connected to the electrode in such a state that the metallic ribbon is deformed toward the inside of the depressed portion.

Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.

Abstract: Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches.

Abstract: A compact ESD protection device is described that uses the reverse breakdown voltage of a base-emitter junction as a trigger diode to switch a transistor that shunts the forward bias ESD current to ground. The trigger diode in series with a leakage diode provides a path to shunt the reverse bias ESD current to ground. The leakage diode is matched to the trigger diode to shunt any leakage current from the trigger diode to ground.

Abstract: A multilayer printed circuit board (PCB) includes a substrate; a ground layer having edges which define a gap portion, the ground layer being provided on a bottom face of the substrate; and at least two signal traces and provided on a top face of the substrate so as to straddle the gap portion and so as to be substantially parallel to each other. The multilayer PCB also includes at least one ground trace provided between the at least two signal traces and on the top face of the substrate so as to straddle the gap portion.