Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.

Abstract: A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded silicon chip is a thin chip (e.g., <50 ?m). In implementations, the wafer-level package device that employs the techniques of the present disclosure includes an active device wafer, a thin integrated circuit chip, an encapsulation structure covering at least a portion of the active device wafer and the thin integrated circuit chip, a redistribution layer structure, and at least one solder bump for providing electrical interconnectivity. Once the wafer is singulated into semiconductor devices, each semiconductor device including the embedded thin integrated circuit chip may be mounted to a printed circuit board.

Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.

Abstract: An integrated circuit package system comprising: forming a substrate having a solder mask with a support structure formed from the solder mask; mounting a first integrated circuit device over the support structure; connecting the substrate and the first integrated circuit device; and encapsulating the first integrated circuit device and the support structure.

Abstract: A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.

Abstract: A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode.

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Abstract: A semiconductor package that includes a conductive clip having an interior surface that includes a plurality of spaced raised portions, a semiconductor device having a first major surface that includes a plurality of spaced depressions each receiving one of the raised portions in the interior thereof, and a conductive adhesive disposed between each raised portion and a respective interior surface of a depression.

Abstract: The laminated high melting point soldering layer includes: a laminated structure which laminated a plurality of three-layered structures, the respective three-layered structures including a low melting point metal thin film layer and a high melting point metal thin film layers disposed on a surface and a back side surface of the low melting point metal thin film layer; a first high melting point metal layer disposed on the surface of the laminated structure; and a second high melting point metal layer disposed on the back side surface of the laminated structure. The low melting point metal thin film layer and the high melting point metal thin film layer are mutually alloyed by TLP, and the laminated structure, and the first high melting point metal layer and the second high melting point metal layer are mutually alloyed by the TLP bonding.

Abstract: A junction body has a first member and a second member each of which is provided with a joining surface whose main component is copper. A solder member containing, in a tin-base solder material, a three-dimensional web structure whose main component is copper is provided between the first member and the second member. A copper-tin alloy whose average thickness is 2 ?m or more but 20 ?m or less is provided between the joining surfaces and the three-dimensional web structure.

Abstract: A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages.

Abstract: A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed in the first opening via an insulating material. At least a through hole passing through the substrate is formed. A metal layer is formed on the upper and lower surface of the substrate and inside the through hole. The metal layer covers the upper and lower surface of the substrate, the heat conducting element and the insulating material. A portion of the metal layer is removed. A solder mask is formed on the metal layer. A surface passivation layer is formed and covers the metal layer exposed by the solder mask and the metal layer located inside the through hole.

Abstract: A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.

Abstract: The semiconductor device according to the present invention includes a semiconductor chip, a solid plate to which the semiconductor chip is bonded, and a bonding member made of a BiSn-based material interposed between the semiconductor chip and the solid plate, while the bonding member has a heat conduction path made of Ag for improving heat conductivity between the semiconductor chip and the solid plate.

Abstract: A conductive connecting sheet (1) of the present invention is composed of a layered body including resin composition layers (11, 13) and a metal layer (12), and each resin composition layer (11, 13) satisfies the following requirement A: in the case where at least a part of metal ball(s) made of the metal material having low melting point is provided within each resin composition layer (11, 13), the metal ball(s) is heated at a temperature which is a melting temperature thereof or higher according to “test methods for soldering resin type fluxes” defined in JIS Z 3197, and then a wet extension of the metal ball(s) is measured, the wet extension is 37% or more.

Abstract: A power block includes an insulating substrate, a conductive pattern formed on the insulating substrate, a power semiconductor chip bonded onto the conductive pattern by lead-free solder, a plurality of electrodes electrically connected to the power semiconductor chip and extending upwardly away from the insulating substrate, and a transfer molding resin covering the conductive pattern, the lead-free solder, the power semiconductor chip, and the plurality of electrodes, wherein surfaces of the plurality of electrodes are exposed at an outer surface of the transfer molding resin and lie in the same plane as the outer surface, the outer surface being located directly above the conductive pattern.

Abstract: The invention relates to a method for fabricating a high-temperature compatible power semiconductor module in which a power semiconductor chip is bonded by means of a diffusion solder layer to a substrate and said substrate is bonded by means of silver sintered layer to a base plate, after which a bonding element is bonded to the top chip metallization. To prevent oxidation of the predefined bond area when producing the diffusion solder layer and the sintered silver layer 4? an anti-oxidation layer is applied to the top chip metallization at least in the region of the predefined bond area.

Abstract: A power block includes an insulating substrate, a conductive pattern formed on the insulating substrate, a power semiconductor chip bonded onto the conductive pattern by lead-free solder, a plurality of electrodes electrically connected to the power semiconductor chip and extending upwardly away from the insulating substrate, and a transfer molding resin covering the conductive pattern, the lead-free solder, the power semiconductor chip, and the plurality of electrodes, wherein surfaces of the plurality of electrodes are exposed at an outer surface of the transfer molding resin and lie in the same plane as the outer surface, the outer surface being located directly above the conductive pattern.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink.

Abstract: A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base.

Abstract: A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.

Abstract: A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.

Abstract: A high melting point soldering layer includes a low melting point metal layer, a first high melting point metal layer disposed on a surface of the low melting point metal layer, and a second high melting point metal layer disposed at a back side of the low melting point metal layer. The low melting point metal layer, the first high melting point metal layer, and the second high melting point metal layer are mutually alloyed by transient liquid phase bonding, by annealing not less than a melting temperature of the low melting point metal layer, diffusing the metal of the low melting point metal layer into an alloy of the first high melting point metal layer and the second high melting point metal layer. The high melting point soldering layer has a higher melting point temperature than that of the low melting point metal layer.

Abstract: The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip. The conductive element has a root portion to hold the rectification chip. The coupling collar is located at one end of the base to hold a package. The coupling collar has a plurality of anchor portions in contact with the package. Each anchor portion has a convex portion and a concave portion extended to two ends of the coupling collar. The convex portion and concave portion of two neighboring anchor portions are formed in a staggered manner. The cross section area of the convex portion on the annular edge of the coupling collar is different from the cross section area of the inner wall of the coupling collar. Hence fabrication and assembly are easier. Turning and loosening of the package can be prevented.

Abstract: In an electronic component soldering method of connecting a terminal provided on a flexible substrate to an electrode of a rigid substrate, after solder-mixed resin in which solder particles are mixed in thermosetting resin has been applied onto the rigid substrate so as to cover the electrode, the flexible substrate is put on the rigid substrate and heat-pressed, whereby there are formed a resin part that bonds the both substrates by thermosetting of the thermosetting resin, and a solder part which is surrounded by the resin part and has narrowed parts in which the peripheral surface is narrowed inward in the vicinity of the terminal surface and in the vicinity of the electrode surface. Hereby, the solder parts are soldered to the electrodes and the terminal at acute contact angles so that the production of shape-discontinuities which lowers fatigue strength can be eliminated.

Abstract: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.

Abstract: This invention relates to a module including a semiconductor chip, at least two contact elements and an insulating material between the two contact elements. Furthermore, the invention relates to a method for production of such a module.

Abstract: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.

Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. The metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Abstract: Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump's elastic modulus is made lower than the elastic modulus of a solder ball.

Abstract: A connection device between two components includes a hollow conductive insert, into which is fitted another conductive insert, the electrical connection between the two inserts being provided by means of a solder element.

Abstract: A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality.

Abstract: A semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material. The filling material fills a gap between the semiconductor chips.

Abstract: A board mounted integrated electronics package assembly is provided with one or more securing elements to attach a heat dissipating device directly to the package. The securing element(s) is located along a periphery of the package and anchors a base of the heat dissipating device to the package, thereby eliminating employment of a secondary heat dissipating material between the package and the heat dissipating device.

Abstract: A semiconductor device includes a semiconductor constituent having a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. An under-layer insulating film is provided under and around the semiconductor constituent. A plurality of under-layer wires are provided under the under-layer insulating film and electrically connected to the electrodes for external connection of the semiconductor constituent. An insulating layer is provided around the semiconductor constituent and on the under-layer insulating film. A frame-like insulating substrate is embedded in an upper surface of the insulating layer and positioned around the semiconductor constituent. A plurality of upper-layer wires are provided on the insulating substrate. A base plate on which the semiconductor constituent and the insulating layer are mounted is removed.

Abstract: A semiconductor device includes a supporting board having a protection film thereon; a semiconductor chip provided on the supporting board; a first internal connecting terminal formed on the supporting board; a second internal connecting terminal formed on the semiconductor chip; a first insulation layer for covering an upper surface of the supporting board and upper and lateral surfaces of the semiconductor chip; a wiring pattern provided on the first insulation layer, the wiring pattern connecting the first and second internal connecting terminals; a solder resist layer provided on the first insulation layer and the wiring pattern, the solder resist layer having an opening part; an external connecting terminal provided so as to connect to the wiring pattern through the opening part; a groove part formed on outer peripheries of the supporting board, the protection film, and the first insulation layer; and a resin layer formed in the groove part.

Abstract: A power block includes an insulating substrate, a conductive pattern formed on the insulating substrate, a power semiconductor chip bonded onto the conductive pattern by lead-free solder, a plurality of electrodes electrically connected to the power semiconductor chip and extending upwardly away from the insulating substrate, and a transfer molding resin covering the conductive pattern, the lead-free solder, the power semiconductor chip, and the plurality of electrodes, wherein surfaces of the plurality of electrodes are exposed at an outer surface of the transfer molding resin and lie in the same plane as the outer surface, the outer surface being located directly above the conductive pattern.

Abstract: Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location.

Abstract: A semiconductor device is provided by the present invention. The semiconductor device includes a first semiconductor die comprising at least a first bond pad; and a second semiconductor die comprising at least a second bond pad with voltage level equivalent to the first bond pad of the first semiconductor die; wherein the first bond pad of the first semiconductor die is electrically connected to the second bond pad of the second semiconductor die via at least a bond wire. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost.

Abstract: An electrical component includes a substrate, component structures on the substrate, and solder metal platings electrically connected to the component structures. The substrate is electrically and mechanically connected in a flip chip arrangement to a carrier via connections formed by solder bumps. The solder bumps mate to the solder metal platings. At least one of the solder bumps is on a first solder metal plating. The first solder metal plating has first and second dimensions, where the first dimension is larger than the second dimension.

Abstract: A novel submount for the efficient dissipation of heat away from a semiconductor light emitting device is described, which also maintains efficient electrical conductivity to the n and p contacts of the device by separating the thermal and electrical conductivity paths. The submount comprises at least the following constituent layers: a substrate (400) with thermally conductive properties; a deposited layer (402) having electrically insulating and thermally conducting properties disposed on at least a region of the substrate having a thickness of between 50 nm and 50 microns; a patterned electrically conductive circuit layer (404) disposed on at least a region of the deposited layer; and, a passivation layer at least partially overcoating a top surface of the submount. Also described is a light emitting module employing the substrate and a method of manufacture of the submount.

Abstract: An embodiment of a die assembly includes a flange, lip walls, and leads for electrical contact with one or more die mounted on the flange. The flange has first and second opposed flange surfaces and flange sidewalls extending between the surfaces. The lip walls have first and second opposed lip surfaces and lip sidewalls extending between the first and second lip surfaces. The lip sidewalls are positioned adjacent to the flange sidewalls. The leads, which have inboard end portions and outboard end portions, are configured to preserve a seating plane. The seating plane is spaced apart from a plane of the second flange surface. The inboard end portions of the leads are embedded in the lip walls, and extend from the seating plane upward through the lip walls toward the first lip surfaces. The outboard end portions are aligned substantially within the seating plane.

Abstract: A semiconductor device includes a bonding pad, and an area designation marking, wherein the bonding pad includes a first region, a second region, and a third region placed between the first region and the second region, wherein the area designation marking includes a first area designation mark configured to designate a first boundary between the first region and the third region and a second area designation mark configured to designate a second boundary between the second region and the third region, wherein the first region and the second region are configured to be contacted with a test probe, The first area designation mark includes a first notch or a first protrusion. The second area designation mark includes a second notch or a second protrusion. The first area designation mark includes a first pair of notches that is linearly spaced apart from each other to designate the first boundary line.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: An electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode. A bonding interface between the first electrode and the second electrode has a multilayer structure including, from the side of the first electrode to the side of the second electrode, (a) a first layer primarily composed of Al, (b) a second layer primarily composed of an Al oxide, (c) a third layer primarily composed of an alloy of Al and a constituent element of metal nanoparticles, and (d) a fourth layer primarily composed of the constituent element of the metal nanoparticles.

Abstract: Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump's elastic modulus is made lower than the elastic modulus of a solder ball.

Abstract: Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer.

Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.

Abstract: A semiconductor system or sensor system in a housing which is butt-joined to a printed circuit board by soldering, at least some of the connecting surfaces not being soldered over their entire area, the connecting surfaces which are not soldered over their entire area being fixedly soldered in a first surface region to a section of a printed conductor, and in a second surface region the connecting surfaces not being fixedly connected to the printed circuit board, the securely soldered surface regions being situated closer to the semiconductor or sensor structure to be contacted than are the surface regions which are not fixedly connected to the printed circuit board.