Abstract: A light emitting diode structure is disclosed that includes a light emitting active portion formed of epitaxial layers and carrier substrate supporting the active portion. A bonding metal system that predominates in nickel and tin joins the active portion to the carrier substrate. At least one titanium adhesion layer is between the active portion and the carrier substrate and a platinum barrier layer is between the nickel-tin bonding system and the titanium adhesion layer. The platinum layer has a thickness sufficient to substantially prevent tin in the nickel tin bonding system from migrating into or through the titanium adhesion layer.
Type:
Grant
Filed:
February 25, 2011
Date of Patent:
August 21, 2012
Assignee:
Cree, Inc.
Inventors:
Matthew Donofrio, David B. Slater, Jr., John A. Edmond, Hua-Shuang Kong
Abstract: A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.
Type:
Grant
Filed:
November 26, 2007
Date of Patent:
July 3, 2012
Assignee:
Infineon Technologies AG
Inventors:
Paul Ganitzer, Francisco Javier Santos Rodriguez, Martin Sporn, Daniel Kraft
Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.
Type:
Application
Filed:
April 2, 2010
Publication date:
August 11, 2011
Inventors:
Wen-Cheng CHIEN, Wen-Ken HUANG, Chien-Hung LIU, Joey LAI
Abstract: A line layout structure and method in a semiconductor memory device having a hierarchical structure are provided. In a semiconductor memory device having a global word line and a local word line, and a global bit line and a local bit line, and individually disposing all of the global word line, the local word line, the global bit line and the local bit line at conductive layers among at least three layers; at least two of the global word line, the local word line, the global bit line and the local bit line are together disposed in parallel on one conductive layer. Signal lines constituting a semiconductor memory device are disposed in a hierarchical structure, whereby a semiconductor memory device advantageously having high integration, high speed and high performance may be obtained.
Type:
Grant
Filed:
July 27, 2009
Date of Patent:
August 9, 2011
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Hyung-Rok Oh, Sang-Beom Kang, Du-Eung Kim
Abstract: A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.
Type:
Grant
Filed:
June 7, 2005
Date of Patent:
October 28, 2008
Assignee:
Micron Technology, Inc.
Inventors:
Gurtej Singh Sandhu, Donald L. Westmoreland