Abstract: A resin molded type semiconductor device has: a semiconductor chip (12) which is mounted on a die pad portion (11) of a lead frame (9); thin metal wires (14) which connect terminals of the semiconductor chip (12) to inner lead portions (13) of the lead frame (9); and a sealing resin (15), and the lead frame (9) is subjected to an upsetting process so that a supporting portion (11) is located at a position higher than the inner lead portions (13). Since the sealing resin of a thickness corresponding to the step difference of the upsetting exists below the supporting portion, the adhesiveness between the lead frame and the sealing resin can be improved, and high reliability and thinning are realized.

Abstract: A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper and lower leads, wherein the upper and lower leads are substantially parallel to the die pad. The upper and lower surfaces of the die pad are attached with upper and lower chips respectively. The upper chip is electrically connected to the upper surface of one part of the upper leads by a plurality of first bonding wires and the lower chip is electrically connected to the lower surfaces of the other part of the upper leads by a plurality of second bonding wires. A sealant is used to encapsulate the chips and bonding wires to protect these elements from damage.

Abstract: A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from the fingers. A chip is disposed on the substrate and is electrically connected to the fingers. An encapsulant is completely filled the peripheral slot. The peripheral slot can enhance the mold flow and eliminate the mold flash. The shape of the dummy metal pattern aligned to the peripheral slot is used to offer stiffening edges to prevent the substrate from warpage and from breakage at peripheries, to enhance the thermal stress resistance due to thermal cycles, and to avoid damages to the chip.

Abstract: A light source having a die carrier, a lead frame, and an insulating body is disclosed. The die carrier includes a die mounting section connected to a heat transfer section. The die mounting section includes a die mounting area having a lead pad opening contained within the die mounting area. The lead frame includes a lead pad. An electrically insulating material fills the voids between the die carrier and the lead frame to maintain the lead frame and die carrier such that a surface of the heat transfer section is exposed on a surface of the body, the lead pad is positioned in the lead pad opening, and the die carrier is electrically isolated from the lead frame. A plurality of dies are attached to the die mounting area and connected to the lead pad.

Abstract: An integrated circuit package system includes providing an integrated circuit die; attaching the integrated circuit die over a lead grid having lead blocks; and connecting a die interconnect to the integrated circuit die and the lead blocks.

Abstract: A semiconductor device comprises: a first and second die pads arranged side by side; a plurality of inner leads arranged around the first and second die pads; first and second chips mounted on the first and second die pads; a bar provided between the first and second chips and the plurality of inner leads, extending in an array direction of the first chip and the second chip; a plurality of wires that connect the first and second chips and the plurality of inner leads and connect the first chip and the second chip; and resin that seals the first and second die pads, the plurality of inner leads, the first and second chips, the plurality of wires and the bar, wherein the bar comprises a mark provided at a position corresponding to an area between the first chip and the second chip in an array direction of the first chip and the second chip.

Abstract: A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chi

Abstract: A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.

Abstract: A semiconductor device includes a semiconductor chip, where the semiconductor chip includes signal contact areas and supply contact areas. The signal contact areas are arranged on edge regions of the active top side of the semiconductor chip and are electrically connected to external signal exterior connections of the semiconductor device by connecting elements. The active top side of the semiconductor chip includes at least two supply collective electrodes made of annularly patterned metal foils which are arranged within the signal contact areas and are affixed in an electrically insulating manner on the top side. The supply collective electrodes are electrically connected to the supply contact areas of the semiconductor chip by internal connecting elements.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip, a solder ball for external connection, wiring for electrically connecting the semiconductor chip and the solder ball, a stress relieving layer provided on the semiconductor chip, and a stress transmission portion for transmitting stress from the solder ball to the stress relieving layer in a peripheral position of an electrical connection portion of the solder ball and wiring.

Abstract: An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. An electronic device with the electronic package is also disclosed.

Abstract: A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads.

Abstract: A light emitting device has a cup portion with a bottom surface opening, and one electrode of a light emitting element is connected to the cup portion. The other electrode of the light emitting element is connected to a lead set up from an inner space to outside the cup portion using the opening of the cup portion. Each electrode and lead of the light emitting device can be electrically connected without bonding wires. This prevents shadows or light unevenness from reflecting the shape of the bonding wire, thereby enhancing light-emission efficiency. As an alternative to setting up the lead from inside to the outside of the cup portion, the lead existing outside the cup portion and the other electrode are electrically connected via the bonding wire through the cup portion's opening. Thus, light outputted outside of the light emitting device is not intercepted by the bonding wire.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: A metal backing tab supports the semiconductor device and has an extending portion extending from an edge. A top leg, a middle leg and a bottom leg are all coupled to the semiconductor device and each has a lead terminal portion extending beyond the boundary of said molded housing. The top leg has a first top leg section that protrudes directly away from the molded housing, a second top leg section that bends toward a direction of a face of the molded housing, and a third top leg section bending downward. The middle leg has a first middle leg section connected to the package that protrudes away from the molded housing, and a middle leg downward section that points downward. The bottom leg has a first bottom leg section that protrudes away from the molded housing face, a second bottom leg section that points away from the molded housing face, and third bottom leg section that points downward.

Abstract: The present invention provides a lead-frame array package structure. The package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads. The first surface and a second surface are composed of the shorter leads and the longer leads. The chip is fixedly connected to the first surface of the lead-frame. The metal pads are positioned on the one side of the active layer of the chip. The metal pads are electrically connected to the leads of the lead-frame via the metal leads. The chip, the metal leads, the first surface and the second surface of the lead-frame is encapsulated by encapsulated material to expose the portion of the metal of the leads. The conductive elements are electrically connected to exposed leads so as to an array arrangement is formed on the second surface of the lead-frame.

Abstract: The invention relates to a substrate with slot. The substrate of the invention comprises an active surface and a plurality of metal plates. The metal plates are formed on the active surface. Each metal plate has a first surface and a second surface. The first surface is connected to the active surface. At least one metal plate has at least one slot formed on the second surface. Therefore, according to the substrate with slot of the invention, a resin for connecting a chip and the metal plates can entirely seal sides and corners of the chip so as to prevent water or dust from entering the chip and protect the chip.

Abstract: The present invention provides a flexible substrate for a package of a die which has an active surface and a plurality of first bond pads arranged in a form of a row and formed on the active surface. The flexible substrate includes a flexible insulating film and a plurality of first leads formed on the flexible insulating film. Each of the first leads corresponds to one of the first bond pads and has a respective first body portion, a respective first bond portion and a respective first extension portion. For each of the first leads, the width of the first bond portion is larger than those of the first body portion and the first extension portion.

Abstract: A method of manufacturing a semiconductor device includes the steps of, (1) preparing a conductive substrate having a main surface and a back surface opposite to the main surface, (2) forming at the main surface of the conductive substrate a plurality of first grooves, which are parallel to each other, and forming at the main surface of the conductive substrate a plurality of second grooves, which are parallel to each other, and which are perpendicular to the first grooves, (3) fixing a semiconductor chip to the main surface of the conductive substrate, (4) encapsulating the semiconductor chip with resin by introducing the resin onto the main surface of the conductive substrate, the resin entering into the first and the second grooves and (5) polishing the back surface of the conductive substrate until the resin formed in the first and the second grooves are exposed.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.

Abstract: A semiconductor package mainly includes a semiconductor chip and a plurality of leads at the periphery of the semiconductor chip. Each of the leads has a first portion, a second portion and opposing upper and lower surfaces, wherein the second portion of the leads are bent upwards. The semiconductor package has a plurality of bonding wires with one ends connected to the bonding pads of the semiconductor chip and the other ends connected to the first portions of the leads. The semiconductor package is provided with a package body formed over the semiconductor chip and the leads, wherein each of the leads is substantially embedded in the package body with the lower surface thereof exposed from the package body. The present invention further provides a method for manufacturing the semiconductor package.

Abstract: An integrated circuit package system including an integrated circuit die, a leadframe and an integrated circuit support. The integrated circuit support between the integrated circuit die and the leadframe with the electrical interconnects connected to the leadframe.

Abstract: A power module package structure is disclosed. The control circuits are fabricated on a circuit plate, instead of fabricating them directly on a main substrate. The fabrication cost is reduced because the size of the substrate is shrunk. Furthermore, the power chips are placed on a material with high thermal conductivity. The heat produced from the power chips can be transmitted quickly. Thus, the reliability of the power module package can be improved.

Abstract: Packaged microelectronic semiconductor devices and methods for their assembly are described. According to preferred embodiments of the invention, chip-on-lead techniques are adapted to provide chip-on-lead packages using cantilevered leads. Exemplary embodiments of the invention include methods using a temporary brace to support the cantilevered leads during chip mounting. Versatile chip package embodiments are disclosed including those in which the chip mounting pad is smaller than the chip(s) mounted thereupon, and further examples wherein the chip mounting pad is dispensed with and a chip is mounted on the cantilevered leads alone.

Abstract: A package for a micro-electromechanical (MEMS) device is described. A premolded leadframe base has opposing top and bottom surfaces. Each surface is defined by a topology having at least one electrically conductive portion and at least one electrically non-conductive portion, and the topology of the top surface differs from the topology of the bottom surface.

Abstract: A semiconductor pressure sensor can reduce the damage of bonding wires to increase their life time even under an environment in which the temperature and pressure change rapidly and radically. The semiconductor pressure sensor includes a package (1) made of a resin and having a concave portion (1a), a lead (2) formed integral with the package (1) by insert molding, with its one end exposed into the concave portion (1a) and its other end extended from the package (1) to the outside, a sensor chip (3) arranged in the concave portion (1a) for detecting pressure, and a bonding wire (4) electrically connecting the sensor chip (3) and the lead (2) with each other. An interface between the lead (2) and the package (1) on the side of the concave portion (1a) is covered with a first protective resin portion (6) of electrically insulating property, and the bonding wire (4) is covered with a second protective resin portion (7) that is softer than the first protective resin portion (6).

Abstract: Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.

Abstract: The present invention provides a package stacking lead frame system comprising forming a lead frame interposer including a dual row of terminal leads positioned around a die attach pad, mounting a first die on the die attach pad, wherein the first die is connected to the dual row of terminal leads, molding a molding compound around the first die and the dual row of terminal leads and mounting a second integrated circuit package on the lead frame interposer, wherein the second integrated circuit package size is independent of the first die size.

Abstract: A semiconductor device (100) with a metal bump (203) on each interior contact pad (202) has a metallic leadframe with lead segments (220) with the first surface (220a) in one plane. The second surface (220b) is castellated across the segment width in two planes so that regions of a first segment thickness (240a) alternate with regions of a reduced (about 50%) second segment thickness (240b); the first thickness regions are in the locations corresponding to the chip interior contact pads (half-etched leadframe). The second segment surface faces the chip so that each first thickness region aligns with the corresponding chip bump. The chip bumps are attached to the corresponding second segment surface using reflow metal. Dependent on the orientation of the attached half-etched segment, thermomechanical stress concentrations away shift from the solder joints into the leadframe metal, or shear stress may reduced.

Abstract: A stamped leadframe for a leadless package and a method of manufacturing the same are provided wherein the leadframe has at least a die pad, a frame, tie bars connecting the die pad to the frame and a plurality of leads. Each lead comprises a first portion and a second portion, and the second portion is connected substantially parallel to and displaced relative to the first portion by a distance that is less than the thickness of the first portion. Portions of the tie-bars and/or die pad may be similarly displaced.

Abstract: In a method and system for fabricating a semiconductor device (200, 300 or 400), a portion of a metal sheet to form a leadframe (210, 310 or 410) having a lead finger (220, 320 or 430) is removed to form a lead finger lock (260, 360 or 460). The lead finger lock (260, 360 or 460) is disposed within a configurable distance of a wirebonding joint (240, 340 or 440) located on a surface of the lead finger (220, 320 or 430). An integrated circuit (IC) chip (290, 390 or 490) is attached to the leadframe (210, 310 or 410). A conductive pad end (232, 332 or 432) of a bond wire (230, 330 or 430) is bonded to the IC chip (290, 390 or 490) and a lead finger end (234, 334 or 434) of the bond wire is bonded to an inner end (222, 322 or 422) of the lead finger at the wirebonding joint (240, 340 or 440). The IC chip, the leadframe, the lead finger, and the wirebonding are encapsulated with a molding compound (MC) (250, 350 or 450).

Abstract: A method of forming a leadframe package, a leadframe package formed according to the method, and a system incorporating the leadframe package. The leadframe package includes: a metallization layer comprising a paddle portion and a contact portion including contact leads; a die mounted onto the paddle portion; wirebonds connected between the die and respective ones of the contact leads; an overmold encapsulating the die, the paddle portion, the contact leads and the wirebonds; and a stiffening element encapsulated in the overmold and unconnected to electrical pathways within the leadframe package.

Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).

Abstract: A semiconductor device of the present invention includes a lead frame having an island portion having a roughened upper surface and side faces, and an unroughened lower surface, and also having a plurality of leads having roughened inner lead portions and unroughened outer lead portions; a semiconductor chip placed on the upper surface of the island portion of the lead frame; a plurality of electrode pads provided on the upper surface of the semiconductor chip; a plurality of wires connecting the plurality of electrode pads and the plurality of leads; and a resin molding the semiconductor chip.

Abstract: An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.

Abstract: A device comprising a semiconductor chip (110) having a side edge (111) and a plurality of metal bond pads (120, 121) near the edge; the pads are aligned to form rows (130, 131) parallel to the edge. The device further includes a leadframe (100) having leads (140 . . . ) oriented with one end (140a . . . ) towards the chip edge and spaced from it by a gap (150); the chip is attached to the leadframe. Ends of selected leads are connected by a metal cross bar (160) parallel to the chip edge. Substantially parallel bond wires (170) are crossing the gap to connect each chip pad either to the crossbar or to a non-selected lead end. In a preferred lead arrangement, the selected leads alternate with non-selected leads.

Abstract: In a semiconductor device (1), semiconductor elements (2) and (3) are mounted on a lead frame (5) having leads (4). The semiconductor elements (2) and (3) are connected with the leads (4) by metallic wires (6) and (7). The semiconductor device (1) also has a heat sink (8). The members (2) to (8) are sealed with a plastic package (10). The leads (4) are exposed outward. Each of the end leads (4a) to (4d) has a wide first lead portion, a narrow second lead portion, a third lead portion to be inserted into an external substrate, and a protruding gap-controlling portion (9) for keeping the gap between the semiconductor device (1) and the external substrate constant. Because the heat resistance from the leads (4) to the plastic package (10) increases, the temperature-rise property of the lead is improved so that the solderability is improved.

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.

Abstract: A method for fabricating a leadframe with encapsulant guide is provided, including forming a die attach paddle. Leads are formed around at least portions of the die attach paddle, and encapsulant guides are formed angled on a plurality of the leads to push the leads outwardly when an encapsulant flows therepast.

Abstract: A semiconductor device which permits reduction in the number of pins and in size thereof is provided.

Abstract: A circuit device is provided comprising leads and electrical circuitry. The circuit device has a first semiconductor element, a second semiconductor element, first leads electrically connected to the first semiconductor element or the second semiconductor element via fine metal wires and having an end thereof extending outwardly, second leads electrically connected via metal wires to both the first semiconductor element and the second semiconductor element to thus electrically connect the first and second semiconductor elements.

Abstract: The present invention discloses a reinforced MEMS package structure, wherein after the wire-bonding process and before the molding process, an extra resin coating process is used to apply a protective resin onto the MEMS chip, the controller chip, the wires and a portion of the lead frame and provide an extra protection for the MEMS structure lest the MEMS structure be damaged by stress, thermal stress, or external force. Thereby, a reinforced MEMS package structure with a higher strength and a smaller size is achieved.

Abstract: The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the outer periphery. The stress-relief means (15) is capable of accommodating expansion and compression while the interlocking means (16) take care of shock and vibration during handling to thereby eliminate delamination of the lead frame (10).

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: An electrical package for an integrated circuit die which comprises a die-attach paddle for mounting the integrated circuit die. The die-attach paddle has at least one down-set area located on a periphery of the die-attach paddle. The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire. A second end of the first electrically conductive lead wire is bonded to the integrated circuit die. The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire and a second end of the second electrically conductive lead wire is bonded to a lead finger of the electrical package.

Abstract: A lead frame comprises a stage for mounting a semiconductor chip thereon, a plurality of leads arranged in the periphery of the stage, and a plurality of lead interconnection members (e.g., dam bars) for interconnecting the leads, wherein a plurality of through holes are formed to penetrate through the lead frame in a thickness direction with respect to the leads or the lead interconnection members so as to allow a plurality of cutting lines to pass therethrough, whereby the leads are subjected to cutting and are made electrically independent of each other. A semiconductor package of a QFN type is produced by enclosing the lead frame within a molded resin, from which the leads are partially exposed to the exterior and are subjected to plating and are then subjected to cutting at the cutting lines.

Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.

Abstract: The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).