Abstract: A semiconductor device includes a lead frame including inner lead portion having inner leads connected to outer leads and relay inner leads not connected to the outer leads. A semiconductor element is mounted on a lower surface of the lead frame. Electrode pads of the semiconductor element are connected to the inner lead portion via metal wire. One end of the relay inner lead is connected to the electrode pad via the metal wire, and the other end is connected to the outer lead via a relay metal wire disposed to step over the inner lead.

Abstract: A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier.

Abstract: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract: This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy.

Abstract: An integrated circuit package system including an integrated circuit die, a leadframe and an integrated circuit support. The integrated circuit support between the integrated circuit die and the leadframe with the electrical interconnects connected to the leadframe.

Abstract: Variations in fastening positions of semiconductor elements are eliminated by forming protrusions on a die pad so as to enclose the semiconductor elements before an adhesive that fastens the semiconductor elements to the die pad is wetted and spread.

Abstract: The present invention relates to a stacked semiconductor package, comprising a carrier, a first semiconductor device, a second semiconductor device, a plurality of first wires and a plurality of second wires. The carrier has a plurality of electrically connecting portions. The first semiconductor device has a plurality of first pads. The second semiconductor device has a plurality of second pads. The second semiconductor device is disposed on the first semiconductor device. The first wires electrically connect the first pads of the first semiconductor device and the electrically connecting portions of the carrier, and the second wires electrically connect the second pads of the second semiconductor device and the electrically connecting portions of the carrier. The diameters of the second wires are larger than those of the first wires. Thus, the material of the wires is reduced, and the manufacturing cost is reduced.

Abstract: A semiconductor device provided with a first semiconductor chip having a first functional surface formed with a first functional element and a first rear surface, a second semiconductor chip having a second functional surface which is formed with a second functional element, the second functional surface having a region opposed to the first functional surface of the first semiconductor chip and a non-opposed region defined outside the opposed region, a connection member electrically connecting the first functional element and the second functional element, an insulation film continuously covering the non-opposed region of the second semiconductor chip and the first rear surface of the first semiconductor chip, a rewiring layer provided on a surface of the insulation film, a protective resin layer covering the rewiring layer, and an external connection terminal projecting from the rewiring layer through the protective resin layer.

Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.

Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.

Abstract: A lead frame includes a lead frame main body having a plurality of die pad portions each having a chip mounting surface on which a semiconductor chip is mounted, a plurality of lead portions provided to surround the plurality of die pad portions respectively, and a frame portion for supporting the plurality of die pad portions and the plurality of lead portions, an adhesive film pasted on a lower surface of the lead frame main body by pressing, and a first metal film provided on surfaces of the plurality of lead portions and connected electrically to the semiconductor chip respectively, wherein second metal films whose thickness is substantially equal to a thickness of the first metal film are provided to the chip mounting surface of the plurality of die pad portions respectively.

Abstract: A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second side opposite to the first side. A second die is attached onto the adhesive. The adhesive fills into the gaps defined by the set of leads. The adhesive is thereafter cured. In a multi-chip integrated circuit package made according to the method, the adhesive attaching the second die fills the gaps between the leads so that to avoid formation of internal cavities of the package.

Abstract: A multi-chip IC package encapsulates a chip under asymmetric longer single-side leads. The package mainly comprises a plurality of leads that have asymmetric length at two sides of a leadframe, a plurality of die-attach tape strips, a first chip having a plurality of single-side pads under the longer side leads, at least a second chip disposed above the longer side leads, a plurality of bonding wires and a molding compound. The die-attach tape strips are mutually parallel and adhered onto the lower surfaces of the longer side leads to adhere the first chip. There is at least a mold-flow channel formed through the first chip, the longer side leads and the die-attach tape strips. The bonding wires electrically connect the single-side pads of the first chip to the leads at the two sides of the leadframe through a non-central gap. The molding compound encapsulates the first chip, the second chip, the bonding wires and portions of the leads at the two sides of the leadframe and fills up the mold-flow channel.

Abstract: A power semiconductor component stack, using lead technology with surface-mountable external contacts, includes at least two MOSFET power semiconductor components each having a top side and an underside. The underside includes: a drain external contact area, a source external contact area and a gate external contact area. The top side includes at least one source external contact area and a gate external contact area. The gate external contact areas on the top side and the underside are electrically connected to one another. The power semiconductor component stack is a series circuit or a parallel circuit of MOSFET power semiconductor components arranged one above another in a plastic housing composition.

Abstract: A housing having a non-detachable bond to a micromechanical component using a flexible bonding material in particular. The combination including the housing and the micromechanical component as well as the manufacturing method of this combination. At least part of the component and/or of the housing has depressions for receiving the bonding material. These depressions may be designed as grooves, for example.

Abstract: The present invention provides a package stacking lead frame system comprising forming a lead frame interposer including a dual row of terminal leads positioned around a die attach pad, mounting a first die on the die attach pad, wherein the first die is connected to the dual row of terminal leads, molding a molding compound around the first die and the dual row of terminal leads and mounting a second integrated circuit package on the lead frame interposer, wherein the second integrated circuit package size is independent of the first die size.

Abstract: A semiconductor die assembly includes a substantially planar lead frame including a die paddle and a plurality of lead fingers, a first semiconductor die secured by an active surface thereof to the die paddle, a second semiconductor die secured by a backside thereof to the die paddle, wire bonds extending from the first semiconductor die and the second semiconductor die to lead fingers of the plurality, and an encapsulant extending over the first semiconductor die, the second semiconductor die, the die paddle, the wire bonds and portions of the lead fingers. A method of fabricating the semiconductor die assembly and an electronic system incorporating the semiconductor die assembly are also disclosed.

Abstract: Packages for an optical integrated circuit die and a method for making such packages are disclosed. The package includes a die, a die pad, a plurality of lead fingers, and an encapsulating dielectric material. The downward second pad surface of the die pad bearing an integrated circuit is encapsulated by a bottom encapsulating dielectric material. The top encapsulating dielectric material provides the function for protecting the leadframe from severe environment. The top encapsulating dielectric material can be neglected if there is no threat on the integrated circuit die and the leadframe. Multiple of lead fingers are mounted on the printed circuit board. A portion of the printed circuit board is removed in order to provide an optical path for the light beam transmitted from a light source through the transparent bottom encapsulating dielectric material into the integrated circuit die. The method of making a package includes forming a leadframe including a die pad and a plurality of lead fingers.

Abstract: A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die. The molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract: The invention provides electronic articles and methods of making said articles. The electronic articles comprise an electronic component bonded and electrically connected to a substrate using an underfill adhesive comprising the reaction product of a thermosetting resin, curing catalyst, and surface-treated nanoparticles that are substantially spherical, non-agglomerated, amorphous, and solid.

Abstract: In one embodiment, a liquid immersion cooled multichip module is provided which includes a substrate having chips mounted thereon and which is adapted to mount with a printed circuit board. A lid is adapted to secure to the printed circuit board so as to mount with the substrate to form a fluid chamber between the lid and the substrate, and to cause the substrate to mate with the printed circuit board. In one embodiment, a cambered bolster plate is located on a side of the printed circuit board opposite the lid and the lid is fastened to the bolster plate to secure the lid to the printed circuit board. A baffle, which may be removable in some embodiments, is located within the lid and directs coolant flow through the fluid chamber.

Abstract: A semiconductor component includes at least one semiconductor power switch, wherein a gate electrode and at least two source regions are disposed on the upper side of the semiconductor power switch. The component further includes a leadframe including a die pad and a number of leads disposed on one side of the die pad. A number of connectors extends between the source regions and the source leads such that each source lead is electrically connected to each source region.

Abstract: A circuit support for a semiconductor chip with a substrate made of an insulating material has a chip mounting area and a plurality of bonding pads surrounding the chip mounting area. The chip can be applied in a central area of the chip mounting area. A peripheral area surrounding the central area defines the border of the chip mounting area and it is of a far greater length than a length of the lateral edges of the chip to be mounted.

Abstract: An LTCC module includes an LTCC substrate and a pad part formed on an undersurface of the LTCC substrate for mounting the LTCC substrate to an external substrate. The pad part includes a metal pad layer formed on an undersurface of the LTCC substrate and a solder layer formed on an undersurface of the metal pad layer.

Abstract: A semiconductor device comprises a substrate, a ferroelectric capacitor which includes a ferroelectric film on the substrate, and a stress application layer which applies tensile or compressive stress to the ferroelectric film of the ferroelectric capacitor by applying stress to the substrate.

Abstract: A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.

Abstract: A junction substrate includes a first substrate, a buffer film formed on one surface of the first substrate, a metal containing film formed on the buffer film and having a lower resistance than the buffer film, and a second substrate bonded to the other surface of the first substrate.

Abstract: A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead frame with target dimple areas, creating dimples in the lead frame corresponding to the gate contact and source contacts, printing a conductive epoxy on the lead frame in the dimples, curing the lead frame and semiconductor die wafer together, and dicing the wafer to form the semiconductor device packages.

Abstract: A solder preform having multiple layers including a solder layer filled with additives interposed between two unfilled layers for improved wettability. A solder preform having a sphere which contains a solder material filled with additives, and an unfilled surface layer for improved wettability. A thermal interface material having a bonding component and an additive component which is a CTE modifying component and/or a thermal conductivity enhancement component. Active solders containing intrinsic oxygen getters.

Abstract: A device and a method for controlling resin bleed, the device comprising a substrate having a surface, wherein an interior region, a peripheral region, and an exterior region of the surface are generally defined. An adhesive generally resides on the surface of the substrate in the peripheral region thereof, wherein the adhesive comprises a plurality of components, such as a metal and a resin. A first barrier is formed on the surface of the substrate generally between the adhesive and the exterior region, wherein the first barrier generally prevents one or more of the plurality of components of the adhesive from bleeding onto the exterior region of the surface of the substrate.

Abstract: A laminated radiation member includes a radiation plate, an insulation substrate bonded to the upper surface of the radiation plate and an electrode provided on the upper surface of the insulation substrate. The laminated radiation member is made by a method including the steps of surface treating a bonding surface of the radiation plate and/or the insulation substrate, interposing ceramic particles surface treated to assure wettability with a hard solder or a metal between the radiation plate and the insulation substrate, disposing a hard solder above and/or below the ceramic particles, heating the hard solder to a temperature higher than the melting point of the solder, penetrating the molten hard solder into spaces between the ceramic particles to react the ceramic particles with the solder to produce a metal base composite material, and bonding the radiation plate and the insulation substrate with the metal base composite material.

Abstract: An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached facedown to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires is attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.

Abstract: A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first surface, a second surface facing opposite the first surface, and a projection extending away from the first surface. A quantity of adhesive material can be applied to the projection to form an attachment structure, and the adhesive material can be connected to a microelectronic substrate with the attachment structure providing no electrically conductive link between the microelectronic substrate and the support member. The microelectronic substrate and the support member can then be electrically coupled, for example, with a wire bond. In one embodiment, the projection can be formed by disposing a first material on a support member while the first material is at least partially flowable, reducing the flowability of the first material, and disposing a second material (such as the adhesive) on the first material.