Abstract: The present invention relates to a fingerprint identifying module, including a circuit board, a fingerprint sensing component, a cover plate, and a waterproof sleeve. The fingerprint sensing component is disposed on the circuit board, and the cover plate covers the fingerprint sensing component. The waterproof sleeve partially covers the cover plate and the circuit board, so as to prevent a foreign liquid from entering a space between the fingerprint sensing component and the circuit board. The cover plate includes a cover plate body and an extending portion. The cover plate body covers the fingerprint sensing component. The extending portion surrounds the cover plate body, is located between the waterproof sleeve and the fingerprint sensing component, and may block the foreign liquid from passing.

Abstract: The invention relates to an electrical device (10), notably intended to control an electric machine, comprising: a first zone filled with an insulating material (A) and comprising a first electronic unit (12) embedded in the insulating material (A); a second zone filled with an insulating material (B) and comprising a second electronic unit (18) embedded in the insulating material (B); and a third zone filled with an insulating material (B) and comprising at least one electrical connection element (22) embedded in the insulating material (B), the at least one electrical connection element (22) connecting the first electronic unit (12) with the second electronic unit (18); in which the first and the second zone are each in contact with the third zone so that the electrical device comprises at least one space extending around the third zone and between the first and the second zone.

Abstract: A gas turbine engine includes a compressor section and a turbine section together defining a core air flowpath. Additionally, a rotary component is rotatable with at least a portion of the compressor section and at least a portion of the turbine section. An electric machine is mounted coaxially with the rotary component and positioned at least partially inward of the core air flowpath along a radial direction of the gas turbine engine. A cavity wall defines at least in part a buffer cavity surrounding at least a portion of the electric machine to thermally insulate the electric machine, e.g., from the relatively high temperatures within the core air flowpath.

Abstract: A power semiconductor device module includes, among other parts, a DMB structure. The DMB structure includes a ceramic sheet, a top metal plate that is directly bonded to the top of the ceramic, and a bottom metal plate that is directly bonded to the bottom of the ceramic. A power semiconductor device die is attached to the top metal plate. The bottom surface of the bottom metal plate has a plurality small cavities. When the bottom metal plate is attached to another metal member, a material between the plate and the member (for example, thermal grease or a PCM or solder) is forced into the cavities. This results in an improvement in thermal transfer between the plate and the member. Such cavities can alternatively, or in addition, be included on a metal surface other than a DMB, such as the bottom surface of a baseplate of the module.

Abstract: The invention relates to an electrical device (10), notably intended to control an electric machine, comprising: a first zone filled with an insulating material (A) and comprising a first electronic unit (12) embedded in the insulating material (A); a second zone filled with an insulating material (B) and comprising a second electronic unit (18) embedded in the insulating material (B); and a third zone filled with an insulating material (B) and comprising at least one electrical connection element (22) embedded in the insulating material (B), the at least one electrical connection element (22) connecting the first electronic unit (12) with the second electronic unit (18); in which the first and the second zone are each in contact with the third zone so that the electrical device comprises at least one space extending around the third zone and between the first and the second zone.

Abstract: Method of encapsulating a semiconductor structure comprising providing a semiconductor structure comprising an opto-electric element located in a cavity formed between a substrate and a cap layer, the cap layer being made of a material transparent to light, and having a flat upper surface; forming at least one protrusion on the cap layer; bringing the at least one protrusion of the cap layer in contact with a tool having a flat surface region, and applying a opaque material to the semiconductor structure where it is not in contact with the tool; and removing the tool thereby providing an encapsulated optical semiconductor device having a transparent window integrally formed with the cap layer.

Abstract: A circuit device comprises a circuit board and a plurality of leads each comprising an island portion, a bonding portion elevated from the island portion, and an oblique slope portion connecting the island portion and the bonding portion, and a plurality of circuit elements mounted on the island portions so as to be connected to corresponding bonding portions through wirings. Two leads are adapted to be connected to positive and negative electrodes of a direct-current power source, and yet another lead is an output lead adapted to output alternating-current power. One electrode provided on a transistor mounted on an island portion of the second input lead is connected to a bonding portion of the output lead through a wiring, and another electrode provided on a transistor mounted on an island portion of the output lead is connected to a bonding portion of the first input lead through a wiring.

Abstract: Method of encapsulating a semiconductor structure comprising providing a semiconductor structure comprising an opto-electric element located in a cavity formed between a substrate and a cap layer, the cap layer being made of a material transparent to light, and having a flat upper surface; forming at least one protrusion on the cap layer; bringing the at least one protrusion of the cap layer in contact with a tool having a flat surface region, and applying a opaque material to the semiconductor structure where it is not in contact with the tool; and removing the tool thereby providing an encapsulated optical semiconductor device having a transparent window integrally formed with the cap layer.

Abstract: A power converter includes a capacitor, a case, and a filler. The case houses the capacitor and includes a metal plate and a partition wall. The filler is interposed between the case and the capacitor. The metal plate is positioned between the capacitor and another electronic component, inside the power converter. Also, the partition wall separates the capacitor from the metal plate.

Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.

Abstract: An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.

Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.

Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.

Abstract: The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane.

Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.

Abstract: A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer.

Abstract: In a semiconductor device including a semiconductor element and a wiring substrate on which the semiconductor element is mounted. The wiring substrate includes an insulating substrate and conductive wiring formed in the insulating substrate and electrically connected to the semiconductor element. The conductive wiring includes an underlying layer formed on the insulating substrate, a main conductive layer formed on the underlying layer, and an electrode layer covering side surfaces of the underlying layer and side surfaces and an upper surface of the main conductive layer. The underlying layer includes an adhesion layer being formed in contact with the insulating substrate and containing an alloy of Ti.

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.

Abstract: A semiconductor device lead frame having enhanced mold locking features is provided. The lead frame has a flag with bendable edge features along the edge of the flag. Each edge feature is shaped to resist movement against encapsulating mold material in a plane of the edge feature. By bending a portion of the edge feature, improved mold locking of the flag is provided in multiple planes.

Abstract: A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.

Abstract: An LED package and a fabrication method therefor. The LED package includes first and second lead frames made of heat and electric conductors, each of the lead frames comprising a planar base and extensions extending in opposed directions and upward directions from the base. The package also includes a package body made of a resin and configured to surround the extensions of the first and second lead frames to fix the first and second lead frames while exposing underside surfaces of the first and second lead frames. The LED package further includes a light emitting diode chip disposed on an upper surface of the base of the first lead frame and electrically connected to the bases of the first and second lead frames, and a transparent encapsulant for encapsulating the light emitting diode chip.

Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.

Abstract: Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a substrate and a plurality of light emitting diodes (LEDs) disposed over the substrate in patterned arrays. The arrays can include one or more patterns of LEDs. A light emitting device can further include a retention material disposed about the array of LEDs. In one aspect, the retention material can be dispensed.

Abstract: A plurality of separate lead frames can be insert-molded in a reflector composed of a white resin having a high reflectivity to form a package for an LED device. A cavity is formed in the reflector. The cavity can have an inner circumferential surface that opens wider in an upward direction. Cups can be located in the cavity. Each cup has an outer wall that can be in the form of a cylinder with the bottom formed of each of two separate lead frames. A red LED chip and a green LED chip can be adhesively fixed to the lead frames located on the bottoms of the respective cups. The LED chips can have lower electrodes, which are electrically brought into conduction with the lead frames one by one. The LED chips can also have upper electrodes, which are electrically brought into conduction with the lead frames one by one via bonding wires. A light transmissive resin can be filled in the cavity.

Abstract: Power module semiconductor packages that contain a flexible circuit board and methods for making such packages are described. The semiconductor package contain a flexible circuit board, a conductive film on a first portion of the upper surface of the flexible circuit board, a land pad on a second portion of the upper surface of the flexible circuit board, a heat sink on a portion of the bottom surface of the flexible circuit board, a passive component, a discrete device, or an IC device connected to a portion of the conductive film, and a lead of a lead frame connected to the land pad. These packages can have a high degree of design flexibility of the layout of the package and simpler routing designs, reducing the time to design the packages and reducing the costs of the packages. Other embodiments are also described.

Abstract: A lead frame enabling simultaneous burn-in testing of plural LEDs while the LEDs are mounted thereon is disclosed. The lead frame according to embodiments of this disclosure may enable burn-in testing of LEDs before packaging.

Abstract: Provided is a simple and low-cost method for manufacturing, in a short time, many light emitting devices wherein adhesiveness between a leadframe and a thermosetting resin composition is high. The method for manufacturing the light emitting device having a resin package (20) wherein the optical reflectivity at a wavelength of 350-800 nm after thermal curing is 70% or more and a resin section (25) and a lead (22) are formed on substantially a same surface on an outer surface (20b) has: a step of sandwiching a leadframe (21) provided with a notched section (21a) by an upper molding die (61) and a lower molding die (62); a step of transfer-molding a thermosetting resin (23) containing a light-reflecting substance (26), in a molding die (60) sandwiched by the upper molding die (61) and the lower molding die (62) and forming a resin-molded body (24) on the leadframe (21); and a step of cutting the resin-molded body (24) and the leadframe (21) along the notched section (21a).

Abstract: A light emission package includes at least one solid state emitter, a leadframe, and a body structure encasing a portion of the leadframe. At least one aperture is defined in an electrical lead to define multiple electrical lead segments, with at least a portion of the aperture disposed outside an exterior side wall of the package. A recess may be defined in the exterior side wall to receive a bent portion of an electrical lead. A body structure cavity may be bounded by a floor, and side wall portions and end wall portions that are separated by transition wall portions including a curved or segmented upper edge, with different wall portions being disposed at different angles of inclination.

Abstract: A light emitting device package is disclosed. The light emitting device package includes a light emitting device disposed on a first lead frame, the light emitting device having an electrode pad on an upper surface thereof, a first wire to electrically interconnect a second lead frame spaced apart from the first lead frame and the electrode pad, and a first bonding ball disposed on the second lead frame, the first bonding ball spaced apart from a first contact point, which is in contact with the first wire and the second lead frame, wherein the first bonding ball is disposed between the first wire and the second lead frame to electrically interconnect the first wire and the second lead frame.

Abstract: A luminous body comprises a transparent plastic moulding with indentations, and LED DIEs disposed within the indentations. One side of each LED DIE lies approximately flush with an upper side of the moulding, and each LED DIE is connected to an electricity supply via electrical conductors disposed on the moulding. A method for producing such a luminous body is also disclosed.

Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.

Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.

Abstract: Several embodiments of microelectronic packages with enhanced heat dissipation and associated methods of manufacturing are disclosed herein. In one embodiment, a microelectronic package includes a semiconductor die having a first side and a second side opposite the first side and a lead frame proximate the semiconductor die. The lead frame has a lead finger electrically coupled to the first side of the semiconductor die. The microelectronic package also includes an encapsulant at least partially encapsulating the semiconductor die and the lead frame. The encapsulant does not cover at least a portion of the second side of the semiconductor die.

Abstract: A microelectronic package includes a mounting structure, a microelectronic element associated with the mounting structure, and a plurality of conductive posts physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts project from the mounting structure in an upward direction, at least one of the conductive posts being an offset post. Each offset post has a base connected to the mounting structure, the base of each offset post defining a centroid. Each offset post also defines an upper extremity having a centroid, the centroid of the upper extremity being offset from the centroid of the base in a horizontal offset direction transverse to the upward direction. The mounting structure is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities may wipe across a contact pad of an opposing circuit board.

Abstract: A manufacturing method of a non-leaded package structure is provided. An upper surface and a lower surface of a metal base plate are patterned so as to form a plurality of first protruding parts and at least a second protruding part on the upper surface and to form a plurality of first recess patterns on the lower surface corresponding to the first protruding parts. A first solder layer is formed in each of the first recess patterns respectively. A chip is mounted on the second protruding part and electrically connected to the first protruding parts with a plurality of bonding wires. An encapsulant is formed on the upper surface. A back etching process is performed on the lower surface to partially remove the metal base plate until the encapsulant is exposed and a lead group including at least a die pad and a plurality of leads is defined.

Abstract: An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.

Abstract: A method for manufacturing an integrated circuit package system includes: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing a bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.

Abstract: An integrated circuit package system includes: a carrier; a device structure in an offset location over the carrier with the device structure having a bond pad and a contact pad; an electrical interconnect between the bond pad and the carrier; an anti-flash structure over the device structure with the anti-flash structure exposing the contact pad; and a package encapsulation adjacent to the anti-flash structure and over the carrier.

Abstract: A system for displaying images is disclosed. A display panel comprises a first substrate and a second substrate with a liquid crystal layer interposed therebetween. A sealant is interposed between the first substrate and a second substrate for sealing the liquid crystal layer. A dielectric layer is overlying the first substrate. Metal lines are overlying the dielectric layer under and/or near the sealant. A planarization layer covers and contacts the dielectric layer and the metal lines to form a first interface between the metal lines and the planarization layer and a second interface between the dielectric layer and the planarization layer. Bridge lines without contacting the planarization layer are disposed under and/or near the sealant, instead of at least a portion of the metal lines contacting the planarization layer.

Abstract: Provided is a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes a package main body with a cavity, a plurality of light emitting diode chips, a wire, and a plurality of lead frames. The plurality of light emitting diode chips are mounted in the cavity. The wire is connected to an electrode of at least one light emitting diode chip. The plurality of lead frames are formed in the cavity, and at least one lead frame is electrically connected to the light emitting diode chip or a plurality of wires.

Abstract: There is provided an LED package having high heat dissipation efficiency. An LED package according to an aspect of the invention may include: a package body including a first groove portion being recessed into the package body and provided as a mounting area on the top of the package body; first and second lead frames arranged on a lower surface of the first groove portion while parts of the first and second lead frames are exposed; an LED chip mounted onto the lower surface of the first groove portion and electrically connected to the first and second lead frames; and a plurality of heat dissipation patterns provided on the bottom of the package body and formed of carbon nanotubes.

Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.

Abstract: A two tier power module has, in one form thereof, a PC board having upper and lower traces with an opening in the insulating material that contains a power device which has upward extending solder bump connections. An upper leadframe is mounted on the solder bumps and the upper tracks of the PC board. Vias in the PC board connect selected upper and lower traces. A control device is mounted atop the leadframe and wire bonded to the leadframe, and the assembly is encapsulated leaving exposed the bottom surfaces of the lower traces of the PC board as external connections. In another form the PC board is replaced by a planar leadframe and the upper leadframe has stepped sections which make connections with the planar leadframe, the bottom surfaces of the planar leadframe forming external connections of the module.

Abstract: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.

Abstract: A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas. The solder balls are disposed on the ball-placement areas.

Abstract: In a side view type light emitting diode (LED) package, a lead frame portion and lead frame electrical contact portions are exposed outside a package body to serve as an additional heat dissipation path. The side view type LED package includes an LED chip, a package body having a side surface with an opening for receiving the LED chip, and lead frames for applying a current to the LED chip. The lead frames include inner leads electrically connected to the LED chip within the package body; electrical contact lower legs extending from the inner leads to a lower portion of the package body and exposed outside the package body in the vicinity of a lower surface of the package body perpendicular to the side surface; and a heat dissipation means extending, separately from the electrical contact lower legs, from at least one of the inner leads outside the package body.

Abstract: The present invention provides a lighting device package with one or more light-emitting elements operatively coupled to a substrate and a frame disposed at least in part around the one or more light-emitting elements. The frame and substrate define a cavity in which the one or more light-emitting elements are positioned, wherein this cavity can be substantially enclosed by an optically transmissive system. At least a portion of the cavity can be filled with an encapsulation material. The frame defines one or more passageways, wherein each passageway interconnects the cavity with the outside through an outside port. For example, the outside port can be accessible from the ambient when the lighting device package is in an assembled state, thereby enabling fluidic movement of the encapsulation material into and/or out of the cavity.

Abstract: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.

Abstract: The present invention provides an integrated circuit package system comprising: attaching a die platform to an integrated circuit die; mounting the integrated circuit die over an external interconnect with a bottom side of the external interconnect partially within the die platform; connecting the integrated circuit die and the external interconnect; and forming an encapsulation over the integrated circuit die with the external interconnect partially exposed.

Abstract: The present invention provides a semiconductor device having a structure which is suitable for reduction in thickness and weight. The semiconductor device 1 comprises a housing 12 which has the recess 24 in the front surface 14, the pair of lead electrodes 20 which have the distal ends 34 exposed in the recess 24, protrude from the external surface of the housing 12 and are bent along the bottom surface 16 of the housing 12, and a semiconductor element 36 which is housed in the recess 24 and is electrically connected to the pair of lead electrodes 20. The housing 12 has the grooves 30 which are formed on the pair of side surfaces 18 which adjoin the front surface 14 and the bottom surface 16 on the right and left sides so as to penetrate the housing 12 from the top surface 28 toward the bottom surface 16 of the housing 12. The grooves 30 preferably have width substantially equal to the thickness of the lead electrode 20.