Abstract: A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. An inventive lead frame features an “up-set” bonding pad electrically connected with the die attach pad and arranged with a bonding support for supporting a plurality of wire bonds. The lead frame also having a large mold flow aperture in the up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.

Abstract: A semiconductor package production method includes the step of die-cutting part of a lead side portion of a seal formed by molding and dam bars using a pedestal and punch. The pedestal has an outer surface at a position retreating from a side surface of an upper seal portion as far as possible and an inner surface generally near a side surface of a lower seal portion. Width Wa of the upper surface of the upper surface of the pedestal is smaller than the overhang size of the upper seal portion. Tip end region Ra of the lead side portion which is present right under the overhang portion of the upper seal portion has a slanted surface Fa1which is sloped inwardly from top to bottom.

Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: Provided is a circuit device capable of increasing the packaging density and preventing the thermal interference between circuit elements to be incorporated. In a hybrid integrated circuit device, a first circuit board and a second circuit board are fitted into a case member in a way that the first circuit board is overlaid with the second circuit board. A first circuit element is arranged on the upper surface of the first circuit board and a second circuit element is arranged on the upper surface of the second circuit board. Furthermore, inside the case member, provided is a hollow portion that is not filled with a sealing resin. Such a configuration prevents the second circuit element, which is a microcomputer, from operating unstably due to a heat generated in the first circuit element, which is a power transistor, for example.

Abstract: An integrated power device module including a lead frame having first and second spaced pads, one or more common source-drain leads located between the first and second pads, and one or more drain leads located on the outside of the second pad. First and second transistors are flip chip attached respectively to the first and second pads, wherein the source of the second transistor is electrically connected to the one or more common source-drain leads. A first clip is attached to the drain of the first transistor and electrically connected to the one or more common source-drain leads. A second clip is attached to the drain of the second transistor and electrically connected to the one or more drain leads located on the outside of the second pad. Molding material encapsulates the lead frame, the transistors, and the clips to form the module.

Abstract: A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.

Abstract: A power semiconductor module and a method of manufacture thereof includes a lead frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.

Abstract: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.

Abstract: A device including a housing for a semiconductor chip is disclosed. One embodiment provides a plurality of leads. A first lead forms an external contact element at a first housing side and extends at the first housing side into the housing in the direction of an opposite second housing side. The length of the first lead within the housing is greater than half the distance between the first and the second housing side.

Abstract: An assembly for a circuit board includes a substrate, at least one circuit component formed on the substrate, and a frame. The frame comprises a first substantially planar surface attached to the substrate, and a hole formed through the frame and defined by a wall that surrounds the at least one circuit component. A method of manufacturing the circuit board includes the step of attaching the substantially planar surface of the frame to the substrate in an arrangement in which the at least one circuit component is surrounded by a wall that defines the hole.

Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.

Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.

Abstract: A power module package includes a power circuit element, a control circuit element, a lead frame, an aluminum oxide substrate having a heat sink and an insulation layer, and a sealing resin. The control circuit element is electrically connected with the power circuit element to control chips within the power circuit element. The lead frame has external connection terminal leads in its edge and has a first surface to which the power circuit element and the control circuit element are attached and a second surface which is used as a heat transmission path. The heat sink is a plate made of metal such as aluminum and the electrical insulation layer is formed at least on an upper surface of the heat sink and made of aluminum oxide. The electrical insulation layer may be formed over an entire surface of the heat sink. Here, the insulation layer is attached to the second surface by an adhesive, on a region below where the power circuit element is attached, to the first surface of the lead frame.

Abstract: A semiconductor component has a leadframe, a semiconductor die and an encapsulation element. The leadframe has a die pad having a first side, at least one lead spaced at a distance from the die pad and at least one support bar remnant protruding from the die pad, each having a distal end. The encapsulation element has plastic and encapsulates at least the semiconductor die and a portion of the first side of the die pad. At least one support bar remnant is positioned within the encapsulation element and the distal end of the support bar remnant is encapsulated by at least one dielectric compound.

Abstract: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.

Abstract: A surface mount semiconductor device using a lead frame can suppress stress applied to a package by a load in a forming process performed for the lead frame projecting from the package at a portion at which the lead frame projects the package. Concave portions can be provided in at least one lead of a pair of leads that project laterally from side faces of the package. The concave portions can be arranged at positions where the leads are bent approximately perpendicularly along the side faces of the package at respective central portions of the leads. Thus, a cross-sectional area of a bending portion of the lead can be reduced, thereby enabling the lead (or leads) to be easily bent with a smaller bending load. Therefore, a surface mount semiconductor device can be achieved which prevents disconnection without impairing a heat radiation property and which has good moisture resistance.

Abstract: A semiconductor package which includes a plurality of leads embedded in a ceramic body, a semiconductor device electrically coupled to the leads, and a molded housing encapsulating at least the semiconductor device.

Abstract: According to one embodiment of the invention, a method of forming a system-in-a-package includes providing a first substrate, coupling a first die to a top surface of the first substrate, coupling one or more surface mount devices to a top surface of a second substrate, coupling the second substrate to a top surface of the first die, interconnecting the first substrate, the second substrate, and the first die, and encapsulating the first die, the second substrate and the surface mount devices.

Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.

Abstract: The present invention relates to a microwave chip supporting structure comprising a first microwave laminate layer, with a first side and a second side, and an outer limit. At least one conductor is formed on said first side extending towards said outer limit. The microwave chip supporting structure further comprises a second microwave laminate layer with a first side and a second side, the second side of the second laminate layer being fixed to at least a part of the first side of the first laminate layer. The first laminate layer and/or the second laminate layer comprises at least one recess arranged for receiving a microwave chip intended to be connected to said conductor. The second laminate layer extends outside the outer limit of the first laminate layer, said conductors continuing on the second side of the second laminate layer without contacting the first laminate layer.

Abstract: An integrated circuit package system includes: providing an interposer having a bond pad and a contact pad; mounting the interposer in an offset location over a carrier with an exposed side of the interposer coplanar with an edge of the carrier; connecting an electrical interconnect between bond pad and the carrier; and forming a package encapsulation over the carrier and the electrical interconnect with both the contact pad and the exposed side of the interposer not covered.

Abstract: A multiple die package for integrated circuits is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A removable storage card package is also described.

Abstract: A metal backing tab supports the semiconductor device and has an extending portion extending from an edge. A top leg, a middle leg and a bottom leg are all coupled to the semiconductor device and each has a lead terminal portion extending beyond the boundary of said molded housing. The top leg has a first top leg section that protrudes directly away from the molded housing, a second top leg section that bends toward a direction of a face of the molded housing, and a third top leg section bending downward. The middle leg has a first middle leg section connected to the package that protrudes away from the molded housing, and a middle leg downward section that points downward. The bottom leg has a first bottom leg section that protrudes away from the molded housing face, a second bottom leg section that points away from the molded housing face, and third bottom leg section that points downward.

Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a metal containment wall and a solder terminal, and a connection joint that electrically connects the routing line and the pad. The metal containment wall includes a cavity, and the solder terminal contacts the metal containment wall in the cavity and is spaced from the routing line.

Abstract: A semiconductor device includes: an insulating tape having a device hole and a plurality of holes; a plurality of leads formed on one surface of the tape and extending at one end into the device hole and at the other end into the holes; a semiconductor chip having a plurality of electrodes on a main surface thereof, being connected with the leads extending into the device hole; an encapsulant formed of an insulating resin, the leads and a predetermined portion of the tape; bump electrodes provided on one surface of the leads; slits provided in the tape between the encapsulant and the bump electrodes and extending along a column of the bump electrodes; and a warp prevention reinforcement made of an insulating film and formed over the tape; wherein the semiconductor chip and the bump electrodes are connected to one and the same surface side of the leads.

Abstract: A white-light emitting device includes a first die and a second die. The first die has a first semiconductor light-emitting layer emitting a first primary color light. The second die has a second semiconductor light-emitting layer emitting a second primary color light, and a third semiconductor light-emitting layer mounted proximate to the second semiconductor light-emitting layer and emitting a third primary color light. The first primary color light is combined with the second and third primary color lights so as to produce white light.

Abstract: A heat dissipation device for electrical components includes an outer surface and an inner surface. The outer surface is configured for mounting the electrical components thereon, wherein the components are mounted to the outer surface to allow the transfer of heat from the electrical components to the heat dissipation device and ambient air. The inner surface defines a cavity within the heat dissipation device that also enables housing of the electrical components.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: An assembly for a circuit board includes a substrate, at least one circuit component formed on the substrate, and a frame. The frame comprises a first substantially planar surface attached to the substrate, and a hole formed through the frame and defined by a wall that surrounds the at least one circuit component. A method of manufacturing the circuit board includes the step of attaching the substantially planar surface of the frame to the substrate in an arrangement in which the at least one circuit component is surrounded by a wall that defines the hole.

Abstract: A semiconductor device having a molded sealing resin for sealing a semiconductor chip on a circuit board thereof reduces resin burrs resulting from the leakage of the sealing resin, and also restrains the occurrence of disconnection caused by a wiring layer being crushed. In the semiconductor device, the sealing resin for sealing the semiconductor chip is molded on the circuit board that has a plurality of wiring patterns and a solder resist for insulatively covering the wiring patterns formed on the front surface thereof, the interval of the wiring patterns is set to range from 50% to 200% of its adjacent interval in a molding line area of the sealing resin.

Abstract: A chip package having a lead frame, a chip, a plurality of bonding wires, and an insulation material is provided. The lead frame comprises a die pad, a plurality of leads, a plurality of signal pads and a plurality of non-signal pads. The signal pads and non-signal pads are underneath the signal leads and non-signal leads respectively. The non-signal pad is directly connected to a non-signal plane in the circuit board through its own vias. The signal pad has a structure which extends toward its adjacent non-signal pads. With the signal pad size enlarged, the capacitance between the non-signal plane in the circuit board and the signal pad is increased. The increased capacitance compensates the inductance induced from the bonding wires and improves the response of the signal propagation path for RF applications.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract: In an electronic circuit device including a substrate including a front surface on which an electronic circuit element is mounted and a reverse surface opposite to the front surface in a thickness direction of the substrate, an electrically conductive terminal member electrically connected to the electronic circuit element, a lead frame extending perpendicular to the thickness direction to face the reverse surface in the thickness direction, and a sealing resin covering at least partially the electronic circuit element, substrate and lead frame while at least a part of the electrically conductive terminal member is prevented from being covered by the sealing resin, the substrate extends to project outward from an end of the lead frame in a transverse direction perpendicular to the thickness direction while the end of the lead frame is covered by the sealing resin.

Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.

Abstract: A micro chip-scale-package system including providing a metal pattern on an adhesion material, attaching an integrated circuit die to the metal pattern, and molding an encapsulant over the integrated circuit die and the metal pattern.

Abstract: A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one another, embedding the components in a flexible material in order to form a flexible holding frame which holds the components, pulling off the film, producing contact-making elements on the exposed side of the components, performing a functional test of the components and, if necessary, repair and/or replacement of components, and fixing and making contact with the components held in the holding frame on the module carrier.

Abstract: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.

Abstract: A radio frequency chip package is formed by assembling a connecting element such as a circuit board or flexible circuit tape having chips thereon with a bottom plane element such as a lead frame incorporating a large thermally-conductive plate and leads projecting upwardly from the plane of the plate. The assembly step places the rear surfaces of the chips on the bottom side of the connecting element into proximity with the thermal conductor and joins the conductive traces on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board. The leads provide robust electrical connections between the connecting element and the circuit board.

Abstract: An integrated circuit package includes a first non-conductive substrate having a first inner surface and a second non-conductive substrate having a second inner surface. A die having a first thickness is disposed between the first and second inner surfaces. A leadframe includes a member having a proximal end and a distal end. The proximal end has a second thickness less than the first thickness. The distal end is disposed between the first and second inner surfaces. The distal end is undulated such that the distal end has an effective thickness greater than the second thickness.

Abstract: A semiconductor chip is mounted on the substrate so that the first group of electrodes faces the first group of leads and the second group of electrodes faces the second group of leads. The first group of leads extends in a direction away from the second group of electrodes. Each of the second group of leads extends so as to pass between the first group of electrodes and is formed to be bent in the region between first and second straight lines.

Abstract: A bump is formed on each element electrode of a semiconductor device, and a thermoplastic resin sheet is aligned in position with the semiconductor device. The sheet and the semiconductor device are subjected to hot pressing to melt the sheet, forming a thermoplastic resin portion that covers a portion other than the end surface of each bump of the semiconductor device. The thermoplastic resin portion obtained after the hot pressing is cut.