Abstract: A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor substrate to a second predetermined thickness, thereby exposing the bottom of the hole.

Abstract: An integrated circuit (IC) device includes a polymer substrate having a topside surface and a bottomside surface opposite the topside surface, a plurality of through-holes that extend from the topside surface to the bottomside surface, and a plurality of bottom metal pads on the bottomside surface positioned over the plurality of through-holes. At least one IC die having an active topside including a plurality of bond pads and a second side is affixed to the topside surface. Bonding features are coupled to the plurality of bond pads for coupling respective ones of the plurality of bond pads to the plurality bottom metal pads. The bonding features extend into the through-holes to contact the bottom metal pads.

Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip having a bonding pad, a metal line electrically connected to the semiconductor chip and having a terminal contacting an external terminal, an insulation layer covering the metal line and having an opening that defines the terminal, and a molding layer molding the semiconductor chip, wherein the molding layer includes a recess pattern exposing the bonding pad and extending from the bonding pad to the terminal, and the metal line is embedded in the recess pattern to contact the bonding pad.

Abstract: A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.

Abstract: The semiconductor device comprises a semiconductor chip and a printed wiring board having a recess in which the semiconductor chip is housed face-down, wherein the printed wiring board comprises multiple wiring layers below a circuit surface of the semiconductor chip on which connection terminals are formed, and the multiple wiring layers include a first wiring layer for forming signal wires, a second wiring layer for forming a ground plane, and a third wiring layer for forming power wires and power BGA and ground BGA pads in sequence from the circuit surface.

Abstract: In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

Abstract: An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.

Abstract: Disclosed herein is a semiconductor package including an electrical device having a first lateral surface; and a core substrate including a cavity in which the electrical device is positioned, wherein the core substrate is inclined in a thickness direction of the core substrate and has a second lateral surface that defines the cavity.

Abstract: There is provided a semiconductor device comprising, a first metal pattern formed at a first metal level and extending in a first direction, a second metal pattern formed at the first metal level, extending in a second direction that is different than the first direction, and disposed on a side of the first metal pattern to be separated from the first metal pattern, a first via structure formed on the first metal pattern, a third metal pattern formed at a second metal level that is different than the first metal level and electrically connected to the first metal pattern by the first via structure, and a first pad electrically connected to the first metal pattern and a second pad electrically connected to the third metal pattern.

Abstract: A method includes forming through vias in a substrate of an array. Nubs of the through vias are exposed from a backside surface of the substrate. A backside passivation layer is applied to enclose the nubs. Laser-ablated artifacts are formed in the backside passivation layer to expose the nubs. Circuit features are formed within the laser-ablated artifacts. By forming the circuit features within the laser-ablated artifacts in the backside passivation layer, the cost of fabricating the array is minimized. More particularly, the number of operations to form the embedded circuit features is minimized thus minimizing fabrication cost of the array.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.

Abstract: Various semiconductor substrates and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor chip on a side of a first substrate. The first substrate has at least one thru-silicon-via. An insulating layer is molded on the side of the first substrate. The insulating layer provides a support structure to enable handling of the first substrate.

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the liner, which is subsequently removed to form an air gap around the conductive material of the through-silicon via. A dielectric layer is formed of the backside of the semiconductor substrate to seal the air gap.

Abstract: A semiconductor device 1 has a semiconductor chip 10. The semiconductor chip 10 is constituted as having a semiconductor substrate 12 and an interlayer insulating film 14 on the semiconductor substrate 12. The semiconductor substrate 12 has a plurality of through electrodes 22 (first through electrodes) and a plurality of through electrodes 24 (second through electrodes) formed therein. On the top surface S1 (first surface) of the semiconductor chip 10, there are provided connection terminals 32 (first connection terminals) and connection terminals 34 (second connection terminals). The connection terminals 32, 34 are connected to the through electrodes 22, 24, respectively. The connection terminals 32 herein are disposed at positions overlapping the through electrodes 22 in a plan view. On the other hand, the connection terminals 34 are disposed at positions not overlapping the through electrodes 24 in a plan view.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract: An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.

Abstract: An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.

Abstract: An electronic device (50) having a conductive substrate via (70) extending between a conductor (39) on a rear face (22) and a conductor (58) over the front surface (23) of the substrate (21) includes a multi-layered etch-stop (56, 56-2) beneath the front surface conductor (58). The etch-stop (56, 56-2) permits use of a single etchant to penetrate both the substrate (21) and any overlying semiconductor (44) and/or dielectric (34) without attacking the overlying front surface conductor (58). This is especially important when the semiconductor (44) and dielectric (34) are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop (56) is preferably a stack (63, 73) of N?2 pairs (62-i) of sub-layers (62-i1, 62-i2) in either order, where a first sub-layer (62-i1) comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer (62-i2) comprises etch resistant material (e.g., Ni).

Abstract: A coplanar waveguide transition includes a substrate, a first coplanar waveguide on a first side of the substrate, and a second coplanar waveguide on a second side of the substrate. The coplanar waveguide transition includes a first, a second, and a third via through the substrate electrically coupling the first coplanar waveguide to the second coplanar waveguide. The coplanar waveguide transition includes voids through the substrate between the first, second, and third vias and edges of the first coplanar waveguide and edges of the second coplanar waveguide.

Abstract: Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via.

Abstract: A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.

Abstract: A semiconductor package structure includes: a substrate comprising a plurality of power supply balls on a first surface of the substrate, a first metal conductor on a second surface of the substrate and at least one via coupling a power supply ball to the first metal conductor of the substrate; a die, comprising a plurality of bond pads on a first surface of the die, a first metal conductor on a second surface of the die and at least one via coupling a bond pad to the first metal conductor of the die; and a plurality of first wire bonds for coupling the first metal conductor of the substrate to the first metal conductor of the die.

Abstract: A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.

Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface and a second surface opposite the first surface. The substrate has a through substrate via extending from the first surface towards the second surface. The first die is attached to the substrate, and the first die is coupled to the first surface of the substrate. The second die is attached to the substrate, and the second die is coupled to the first surface of the substrate. A first distance is between a first edge of the first die and a first edge of the second die, and the first distance is in a direction parallel to the first surface of the substrate. The first distance is equal to or less than 200 micrometers.

Abstract: A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by an isolation layer, a first external pad, and a via contact contacting the current rail with the first external pad.

Abstract: A structural member for use in semiconductor packaging is disclosed. The structural member includes a plurality of packaging regions to facilitate packaging dies in, for example, a wafer format. A packaging region has a die attach region surrounded by a peripheral region. A die is attached to the die attach region. In one aspect, the die attach region has opening through the surfaces of the structural member for accommodating a die. Through-vias disposed are in the peripheral regions. The structural member reduces warpage that can occur during curing of the mold compound used in encapsulating the dies. In another aspect, the die attach region does not have an opening. In such cases, the structural member serves as an interposer between the die and a substrate.

Abstract: A method for manufacturing a semiconductor package includes the steps of forming first circuit patterns on an upper surface of a carrier substrate. Bumps are formed in recesses defined on the upper surface of the carrier substrate. An insulation layer is formed on the upper surface of the carrier substrate to cover the first circuit patterns. Second circuit patterns are formed on an upper surface of the insulation layer so as to be electrically connected with the first circuit patterns. The carrier substrate is then separated from the insulation layer.

Abstract: A wafer level molding structure including a first chip, a second chip and an adhesive layer therebetween is provided. The first chip includes a first back side, a first front side and a plurality of lateral sides, and a plurality of first front side bumps are disposed on the first front side. The second chip includes a second back side and a second front side, and a plurality of second back side bumps and second front side bumps are respectively disposed on the second back side and the second front side. A plurality of through electrodes are disposed in the second chip, and electrically connected the second back side bumps to the second front side bumps. Adhesive materials including a plurality of conductive particles cover the lateral sides, and electrically connect the second back side bumps with the first front side bumps.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other.

Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure includes a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.

Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Abstract: A microelectronic device includes a substrate including a via hole extending therethrough, a porous layer on sidewalls of the via hole, and a conductive via electrode extending through the via hole between the sidewalls thereof. The porous layer includes a plurality of pores therein that reduce a dielectric constant of the porous layer. Related fabrication methods are also discussed.

Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Abstract: A semiconductor package having a first semiconductor device including an active surface and a non-active surface opposite to the active surface, and a second semiconductor device having an active surface facing the active surface of the first semiconductor device is provided. Connection terminals are provided on the active surface of the second semiconductor device and first through vias are provided in the first semiconductor device. External terminals providing electrical connection with an external device are provided. The connection terminals comprise center terminals overlapping with the active surface of the first semiconductor device and outer terminals around the center terminals. The center terminals are electrically connected to the external terminals through the first through via.

Abstract: A package on package (PoP) employing a through substrate via (TSV) technique in order to reduce the size of a semiconductor chip, has vertically narrow pitches, and forms a higher number of connection terminals. The PoP include a first substrate with a recess disposed in a first surface of the substrate, and a semiconductor chip disposed at the recess. The PoP also includes a semiconductor package connected to the first semiconductor package. The first substrate includes TSVs for electronically connecting the semiconductor package and the semiconductor chip, and routing lines for re-distributing the signals/and or power transmitted via the TSVs.

Abstract: Apparatus including a chip substrate having a first chip surface facing away from a second chip surface; an array of microelectronic elements on the first chip surface; and an array of conductors each in communication with one of the microelectronic elements, the conductors passing through the chip substrate and fully spanning a distance between the first and second chip surfaces.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a first surface and a second surface, the second surface is on the opposite side of the substrate facing away from the first surface. The method further includes forming a first portion of an opening by etching a portion of the substrate from the first surface, forming a buffer layer on an inner surface of the first portion, etching a bottom of the buffer layer to expose an area of the underlying substrate, and etching the exposed area of the substrate to form a second portion of the opening. The method also includes performing an isotropic etching on the second portion of the opening to obtain a flask-shaped opening and filling the opening with a filling material. The method also includes partially removing a portion of the second surface and the filling material from the second portion of the opening.

Abstract: A packaged integrated circuit includes a substrate having a wire layout pattern and a solder mask layer. An integrated circuit attached to a surface of the substrate is electrically connected to the wire layout pattern. An encapsulation material covers at least the integrated circuit and the solder mask layer. One or more crack seal rings are disposed on the solder mask surface. The crack seal rings are copper traces with terminals that allow current to be applied to the traces. A broken trace (open circuit condition) is indicative of a crack in the package. Thus, electrical testing is performed to detect physical defects.

Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.

Abstract: The present disclosure discloses a COF (Chip On Film), the plane shape of which is a non-orthogonal parallelogram. The present disclosure further discloses a COF carrier tape, which includes a COF tape formed by orderly connecting several COF and a carrier connected with said COF tape. The plane shape of said COF is a non-orthogonal parallelogram. Said COF includes two paralleled wiring edges, and the two adjacent wiring edges of said COF are mutually connected. The present disclosure also discloses a drive circuit for liquid crystal display television. With the COF wiring number increased, the wiring intervals of the present disclosure remain unchanged. When the wiring number of COF are no longer increased, the lengths of the wiring edges can be shortened if the intervals remain unchanged; as a result, the total area of COF can reduced so that the cost can be effectively lowered.

Abstract: A method for fabricating a semiconductor device is provided which includes providing a first device, a second device, and a third device, providing a first coating material between the first device and the second device, the first coating material being uncured, providing a second coating material between the second device and the third device, the second coating material being uncured, and thereafter, curing the first and second coating materials in a same process.

Abstract: In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

Abstract: A memory device comprising a plurality of tunnel junctions (TJs) includes a bottom wiring layer; a top wiring layer; a plurality of TJs contacting the bottom wiring layer and the top wiring layer; and a plurality of tunnel junction vias (TJVs) contacting the bottom wiring layer and the top wiring layer, wherein the plurality of TJVs each have a lower resistance the each of the plurality of TJs, wherein the plurality of TJVs comprise at least one concave surface, and wherein the at least one concave surface of the plurality of TJVs is configured to trap etched material during formation of the TJVs so as to reduce the resistance of the plurality of TJVs.

Abstract: An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.

Abstract: Disclosed is a semiconductor device having improved heat dissipation efficiency. The semiconductor device includes a silicon interposer having a first surface and a second surface opposite the first surface. A plurality of semiconductor chips are provided on the first surface side of the silicon interposer. The silicon interposer has a plurality of via holes extending from the first surface to the second surface. An N type semiconductor and a P type semiconductor constituting a Peltier element are provided in each two of the via holes.