Abstract: The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cerium oxide and titanium oxide. The dielectric materials can be incorporated into any suitable semiconductor devices, including, for example, capacitor devices, transistor devices, and flash memory devices. The invention also includes methods of utilizing atomic layer deposition to form laminates of cerium oxide and titanium oxide.

Abstract: One embodiment of the present invention is a method for fabricating a low-k dielectric film that included steps of: (a) chemical vapor depositing a lower-k dielectric film; and (b) e-beam treating the lower-k dielectric film.

Abstract: A conductor pattern is formed on a resin film which is made of a thermoplastic resin. Each single-sided conductor pattern film has via-holes filled with an electrically conductive paste. A printed conductor pattern and a printed resistor are formed on a ceramic substrate. The single-sided conductor pattern films are laminated on the ceramic substrate. Then, the multilayered assembly is heated and pressed from both sides thereof to obtain a printed circuit board. During the heat and press treatment, respective single-sided conductor pattern films and the ceramic substrate bond together while the interlayer connection is obtained between the conductor patterns as well as between the conductor pattern and the printed conductor pattern.

Abstract: A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection structure is disposed on the chip, and the first pads of the chip are electrically coupled to the interconnection structure. The second pads are disposed on the interconnection structure, and the panel-shaped component is embedded in the interconnection structure. The panel-shaped component also includes a plurality of electrodes on its two opposite surfaces, and the second pads are electrically coupled to the first pads of the chip through the interconnection structure and the panel-shaped component.

Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.

Abstract: A low relative permittivity SiOx film excellent in heat resistance without using an alkali metal, fluorine, etc., a method for modifying an SiOx film to accomplish a further reduction of the relative permittivity of the low relative permittivity SiOx film and further to increase the insulating property, a highly reliable semiconductor device free from crack or peeling of the film by employing the low relative permittivity SiOx film as an interlayer insulating film for metal wirings, are provided. The low relative permittivity film is characterized in that it is made of a porous material, the major constituent of which is SiOx (where 1.8?X?1.0), and the relative permittivity at 1 MHz is at most 2.3.

Abstract: An organic-framework zeolite interlayer dielectric is disclosed. The interlayer dielectric's resistance to chemical attack, its dielectric constant, its mechanical strength, or combinations thereof can be tailored by (1) varying the ratio of carbon-to-oxygen in the organic-framework zeolite, (2) by including tetravalent atoms other than silicon at tetrahedral sites in the organic-framework zeolite, or (3) by including combinations of pentavalent/trivalent atoms at tetrahedral sites in the organic-framework zeolite.