Characterized By Materials (epo) Patents (Class 257/E23.072)
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Patent number: 11696410Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate is first prepared. The seeded substrate includes an insulation substrate, a conductive undercoat layer having a hydrophilic surface and provided on the insulation substrate, a conductive seed layer provided on a first region of the surface of the undercoat layer, the first region having a predetermined pattern, and a water-repellent layer on the second region of the surface of the undercoat layer, the second region being a region other than the first region. Subsequently, a metal layer is formed on the seed layer. A voltage is applied between the anode and the seed layer while a solid electrolyte membrane being disposed between the seeded substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the water-repellent layer and the undercoat layer are etched.Type: GrantFiled: May 19, 2021Date of Patent: July 4, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki Kondoh, Rentaro Mori, Hiroshi Yanagimoto, Keiji Kuroda, Kazuaki Okamoto
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Patent number: 11574873Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.Type: GrantFiled: August 26, 2020Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sunkyoung Seo, Taehwan Kim, Hyunjung Song, Hyoeun Kim, Wonil Lee, Sanguk Han
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Patent number: 11017950Abstract: A ceramic electronic component includes a ceramic body, an inner electrode, an outer electrode, and a connecting portion. The inner electrode is disposed inside the ceramic body. The end portion of the inner electrode extends to a surface of the ceramic body. The outer electrode is disposed on the surface of the ceramic body so as to cover the end portion of the inner electrode. The outer electrode includes a resin and a metal. The connecting portion is disposed so as to extend from an inside of the outer electrode to an inside of the ceramic body. In a portion of the surface of the ceramic body on which the outer electrode is disposed, the length of the connecting portion that extends in a direction in which the inner electrode is extends about 2.4 ?m or more.Type: GrantFiled: September 22, 2016Date of Patent: May 25, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kota Zenzai, Hisayoshi Omori, Takashi Kanayama, Kiyoyasu Sakurada, Naoki Shimizu, Seiji Katsuta, Shinji Otani
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Patent number: 10361178Abstract: In an embodiment, an interconnection structure includes a first semiconductor device including a conductive stud, a second device including a contact pad, an adhesive layer including an organic component arranged between a distal end of the conductive stud and the contact pad, the adhesive layer coupling the conductive stud to the contact pad, and a conductive layer extending from the conductive stud to the contact pad. The conductive layer has a melting point of at least 600° C.Type: GrantFiled: September 29, 2015Date of Patent: July 23, 2019Assignee: Infineon Technologies Austria AGInventor: Martin Standing
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Patent number: 9918388Abstract: A circuit substrate includes: a mounting region having an exposed surface that is planarized, and in which a predetermined chip is to be mounted; patterns provided in the mounting region, and including respective top faces that form a part of the exposed surface; and solder bumps provided on the respective patterns, and having substantially same shape as one another.Type: GrantFiled: December 18, 2013Date of Patent: March 13, 2018Assignee: SONY CORPORATIONInventor: Hiroshi Asami
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Publication number: 20140027915Abstract: In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.Type: ApplicationFiled: July 24, 2012Publication date: January 30, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Thomas GRILLE, Ursula Hedenig, Joern Plagmann, Helmut Schoenherr, Ralph Muth
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Patent number: 8637983Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.Type: GrantFiled: December 19, 2008Date of Patent: January 28, 2014Assignee: ATI Technologies ULCInventors: Liane Martinez, Roden R. Topacio, Yip Seng Low
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Publication number: 20130307156Abstract: A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.Type: ApplicationFiled: May 15, 2012Publication date: November 21, 2013Applicant: INFINEON TECHNOLOGIES AGInventor: Reinhold Bayerer
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Patent number: 8575625Abstract: A semiconductor element mounting member is arranged to infiltrate a matrix metal into a porous body that is formed by sintering diamond particles being in direct contact with each other and that has an infiltration auxiliary layer selectively formed only on the exposed surface of each diamond particle. A production method includes a step at which a mixture of diamond particles, a powder of a chemical element out of which the infiltration auxiliary layer is made, and an ammonium chloride powder is compressed and molded, is then heated to 900° C. or more, and is formed into the porous body. A semiconductor device has a semiconductor element mounted on an element mounting surface of the semiconductor element mounting member with a connecting layer therebetween.Type: GrantFiled: August 1, 2012Date of Patent: November 5, 2013Assignee: A.L.M.T. Corp.Inventors: Kouichi Takashima, Yoshifumi Aoi, Eiji Kamijo
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Publication number: 20130112993Abstract: A semiconductor device according to one embodiment of the present invention includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate and having a conductive property, and a semiconductor element mounted on the wiring layer. In the semiconductor device, the insulating substrate is composed of cBN or diamond.Type: ApplicationFiled: October 26, 2012Publication date: May 9, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventor: Sumitomo Electric Industries, Ltd.
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Publication number: 20130105980Abstract: Disclosed is a sinterable bonding material which is a liquid or a paste containing copper nanoparticles having a particle diameter of 1,000 nm or less, in which the copper nanoparticles have one or more particle diameter peaks of a number-based grain size distribution within a class of particle diameter of 1 to 35 nm and within a class of particle diameter of more than 35 nm and 1,000 nm or less respectively, and in which the copper nanoparticles include individual particles (primary particles) and secondary particles, each of the secondary particles being a fused body of the primary particles. Thus, oxidation resistance and bondability are made compatible in a sinterable bonding material using copper nanoparticles, and ion migration is suppressed in a bonded portion of a semiconductor device, etc. manufactured by using the sinterable bonding material.Type: ApplicationFiled: October 24, 2012Publication date: May 2, 2013Applicant: HITACHI, LTD.Inventor: Hitachi, Ltd.
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Patent number: 8399996Abstract: Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location.Type: GrantFiled: August 5, 2011Date of Patent: March 19, 2013Assignee: Infineon Technologies AGInventors: Khalil Hosseini, Joachim Mahler
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Patent number: 8395265Abstract: The present invention provides metal silicide nanowires, including metallic, semiconducting, and ferromagnetic semiconducting transition metal silicide nanowires. The nanowires are grown using either chemical vapor deposition (CVD) or chemical vapor transport (CVT) on silicon substrates covered with a thin silicon oxide film, the oxide film desirably having a thickness of no greater than about 5 nm and, desirably, no more than about 2 nm (e.g., about 1-2 nm). The metal silicide nanowires and heterostructures made from the nanowires are well-suited for use in CMOS compatible wire-like electronic, photonic, and spintronic devices.Type: GrantFiled: July 2, 2010Date of Patent: March 12, 2013Assignee: Wisconsin Alumni Research FoundationInventors: Song Jin, Andrew L. Schmitt, Yipu Song
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Publication number: 20130049204Abstract: A semiconductor device includes a substrate and a first sintered silver layer on the substrate. The semiconductor device includes a first semiconductor chip and a first diffusion soldered layer coupling the first semiconductor chip to the first sintered silver layer.Type: ApplicationFiled: August 22, 2011Publication date: February 28, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Niels Oeschler, Kirill Trunov, Roland Speckels
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Publication number: 20130037957Abstract: A flux composition includes an alditol (A) and a polymer (B) which has a repeating structural unit represented by Formula (1): (wherein R1 is a hydrogen atom or a methyl group, and Z is a hydroxyl group, an oxo group, a carboxyl group, a formyl group, an amino group, a nitro group, a mercapto group, a sulfo group, an oxazoline group, an imide group, a group having an amide structure, or a group having any of these groups). The flux composition allows substrates with bumps such as pillar bumps to be electrically connected to each other by reflowing of such bumps without causing any exposure of the bumps from the flux during reflowing, thus resulting in a satisfactory electrically connected structure.Type: ApplicationFiled: June 1, 2012Publication date: February 14, 2013Applicant: JSR CORPORATIONInventors: Seiichirou TAKAHASHI, Torahiko YAMAGUCHI, Hirofumi GOTO
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Publication number: 20130009311Abstract: A semiconductor package includes: a first encapsulant having tapered through holes each having a wide top and a narrow bottom; tapered electrical contacts disposed in the tapered through holes; circuits disposed on a top surface of the first encapsulant and each having one end connecting one of the electrical contacts and the other end having a bonding pad disposed thereon such that the bonding pads are circumferentially arranged to define a die attach area on the top surface of the first encapsulant. As such, a semiconductor chip can be disposed on the top surface of the first encapsulant in the die attach area and electrically connected to the bonding pads through conductive elements, and further a second encapsulant encapsulates the semiconductor chip, the conductive elements, the circuits and the first encapsulant so as to prevent falling off of the electrical contacts and reduce the length of the conductive elements.Type: ApplicationFiled: December 1, 2011Publication date: January 10, 2013Applicant: Siliconware Precision Industries Co., Ltd.Inventors: Pang-Chun Lin, Yueh-Ying Tsai, Yong-Liang Chen
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Publication number: 20130001787Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on the semiconductor substrate; a first metal ring surrounding the semiconductor element; an insulation film formed to cover the semiconductor element and having the first metal ring disposed therein; and a groove formed in the insulation film; wherein: the first metal ring is formed by laminating multiple metal layers in such a manner that respective outside lateral faces of the multiple metal layers are flush with each other, or that outside lateral face of each of the multiple metal layers which is positioned above an underlying metal layer is positioned more inside than outside lateral face of the underlying metal layer; and the groove has first bottom which is disposed inside the first metal ring and extending to a depth of upper surface of an uppermost metal layer of the first metal ring.Type: ApplicationFiled: April 16, 2012Publication date: January 3, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazutaka Yoshizawa, Taiji Ema
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Publication number: 20120313198Abstract: A lead-free paste composition contains an electrically conductive silver powder, one or more glass frits or fluxes, and a lithium compound dispersed in an organic medium. The paste is useful in forming an electrical contact on the front side of a solar cell device having an insulating layer. The lithium compound aids in establishing a low-resistance electrical contact between the front-side metallization and underlying semiconductor substrate during firing.Type: ApplicationFiled: December 8, 2011Publication date: December 13, 2012Applicant: E. I. DU PONT DE NEMOURS AND COMPANYInventors: Steven Dale Ittel, Zhigang Rick Li, Kurt Richard Mikeska, Paul Douglas Vernooy
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Publication number: 20120299180Abstract: A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.Type: ApplicationFiled: August 2, 2012Publication date: November 29, 2012Inventors: Yu-Ju Yang, Chih-Hung Lu
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Publication number: 20120292769Abstract: A semiconductor element mounting member is arranged to infiltrate a matrix metal into a porous body that is formed by sintering diamond particles being in direct contact with each other and that has an infiltration auxiliary layer selectively formed only on the exposed surface of each diamond particle. A production method includes a step at which a mixture of diamond particles, a powder of a chemical element out of which the infiltration auxiliary layer is made, and an ammonium chloride powder is compressed and molded, is then heated to 900° C. or more, and is formed into the porous body. A semiconductor device has a semiconductor element mounted on an element mounting surface of the semiconductor element mounting member with a connecting layer therebetween.Type: ApplicationFiled: August 1, 2012Publication date: November 22, 2012Inventors: Kouichi Takashima, Yoshifumi Aoi, Eiji Kamijo
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Publication number: 20120267770Abstract: A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.Type: ApplicationFiled: July 3, 2012Publication date: October 25, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Paul Ganitzer, Francisco Javier Santos Rodriguez, Martin Sporn, Daniel Kraft
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Patent number: 8294269Abstract: An electronic structure may include a conductive pad on a substrate, and an insulating layer on the substrate and on the conductive pad. The insulating layer may have a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer. A conductive layer comprising copper may be on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on surface portions of the insulating layer surrounding the via opposite the substrate and the conductive pad, and the conductive layer comprising copper may have a thickness of at least approximately 1.0 ?m. A conductive barrier layer may be on the conductive layer comprising copper, and the conductive barrier layer may include at least one of nickel, platinum, palladium, and/or combinations thereof.Type: GrantFiled: December 8, 2010Date of Patent: October 23, 2012Assignee: Unitive InternationalInventors: Krishna K. Nair, Glenn A. Rinne, William E. Batchelor
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Publication number: 20120261819Abstract: A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.Type: ApplicationFiled: April 3, 2012Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Brunschwiler, Javier V. Goicochea, Cyrill Kuemin, Walter H. Riess, Heiko Wolf
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Patent number: 8288868Abstract: A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.Type: GrantFiled: March 12, 2012Date of Patent: October 16, 2012Assignee: Stanley Electric Co., Ltd.Inventor: Toshihiro Seko
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Publication number: 20120223434Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.Type: ApplicationFiled: May 14, 2012Publication date: September 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, John A. Fitzsimmons
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Patent number: 8212349Abstract: A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip.Type: GrantFiled: December 29, 2009Date of Patent: July 3, 2012Assignee: Powertech Technology Inc.Inventors: Hung-Hsin Hsu, Chin-Ming Hsu, Jui-Ching Hsu
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Publication number: 20120153444Abstract: A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.Type: ApplicationFiled: June 17, 2010Publication date: June 21, 2012Applicant: ROHM CO., LTDInventors: Motoharu Haga, Shingo Yoshida, Yasumasa Kasuya, Toichi Nagahara, Akihiro Kimura, Kenji Fujii
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Publication number: 20120139117Abstract: A semiconductor device includes a workpiece and a first material layer disposed over the workpiece. The first material layer has a first number of atoms at a surface. A seed layer is disposed over the first material layer. The seed layer includes a chemisorbed monolayer of a second number of atoms at the surface having a surface coverage of at least 0.5 such that the ratio of the number of first atoms at the surface to the number of second atoms at the surface is no more than 2:1. The second atoms of the seed layer include oxygen or nitrogen.Type: ApplicationFiled: February 9, 2012Publication date: June 7, 2012Applicant: INFINEON TECHNOLOGIES AGInventor: Stefan Wurm
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Publication number: 20120086122Abstract: The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process.Type: ApplicationFiled: October 12, 2010Publication date: April 12, 2012Inventors: BIN-HONG CHENG, MENG-JEN WANG
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Patent number: 8154129Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.Type: GrantFiled: April 4, 2008Date of Patent: April 10, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Kikuo Okada, Kojiro Kameyama, Takahiro Oikawa
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Publication number: 20110315210Abstract: The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells.Type: ApplicationFiled: December 17, 2010Publication date: December 29, 2011Applicant: E. I. DU PONT DE NEMOURS AND COMPANYInventors: Kenneth Warren Hang, Daniel Kirk, Brian J. Laughlin, Ben Whittle
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Patent number: 8072068Abstract: A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface.Type: GrantFiled: May 20, 2009Date of Patent: December 6, 2011Assignee: Rohm Co., Ltd.Inventor: Tatsuya Sakamoto
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Publication number: 20110285033Abstract: Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location.Type: ApplicationFiled: August 5, 2011Publication date: November 24, 2011Applicant: Infineon Technologies AGInventors: Khalil Hosseini, Joachim Mahler
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Publication number: 20110254151Abstract: A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.Type: ApplicationFiled: April 16, 2010Publication date: October 20, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Wei LIN, Ming-Da CHENG, Wen-Hsiung LU, Chung-Shi LIU
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Publication number: 20110187000Abstract: An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.Type: ApplicationFiled: April 11, 2011Publication date: August 4, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Jeffrey A. WEST
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Publication number: 20110156238Abstract: A semiconductor package having chip using copper process is revealed. A chip using copper process is disposed on a substrate. The substrate has a core layer, a copper circuitry with connecting pads, a patterned diffusion barrier, and a solder mask. The copper circuitry is formed on the core layer. The patterned diffusion barrier has such a pattern identical to the one of the copper circuitry that an upper surface of the copper circuitry is completely covered. The substrate further has a bonding layer formed on a portion of the patterned diffusion barrier inside the solder mask's opening. Therefore, diffusion of copper ions from the copper circuitry of the substrate to the active surface of the chip can be avoided to prevent function failure of the chip.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Inventors: Hung-Hsin Hsu, Chin-Ming Hsu, Jui-Ching Hsu
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Publication number: 20110156260Abstract: An integrated circuit chip includes a substrate; a topmost metal layer overlying the substrate; and a pad in the topmost metal layer. A thickness of the pad is less than a thickness of the topmost metal layer.Type: ApplicationFiled: October 27, 2010Publication date: June 30, 2011Inventor: Yu-Hua Huang
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Publication number: 20110101523Abstract: A copper pillar bump has a surface covered with by a barrier layer formed of a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. The barrier layer depresses the copper diffusion and reaction with solder to reduce the thickness of intermetallic compound between the pillar pump and solder.Type: ApplicationFiled: November 5, 2010Publication date: May 5, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Ling HWANG, Yi-Wen WU, Chung-Shi LIU
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Publication number: 20110101533Abstract: A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers.Type: ApplicationFiled: November 3, 2009Publication date: May 5, 2011Inventors: Sang Won Yoon, Alexandros Margomenos
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Patent number: 7928575Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.Type: GrantFiled: May 14, 2009Date of Patent: April 19, 2011Assignee: Kobe Steel, Ltd.Inventors: Hiroshi Gotoh, Toshihiro Kugimiya, Junichi Nakai, Katsufumi Tomihisa
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Publication number: 20110084392Abstract: An electronic structure may include a conductive pad on a substrate, and an insulating layer on the substrate and on the conductive pad. The insulating layer may have a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer. A conductive layer comprising copper may be on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on surface portions of the insulating layer surrounding the via opposite the substrate and the conductive pad, and the conductive layer comprising copper may have a thickness of at least approximately 1.0 ?m. A conductive barrier layer may be on the conductive layer comprising copper, and the conductive barrier layer may include at least one of nickel, platinum, palladium, and/or combinations thereof.Type: ApplicationFiled: December 8, 2010Publication date: April 14, 2011Inventors: Krishna K. Nair, Glenn A. Rinne, William E. Batchelor
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Patent number: 7902056Abstract: Devices and methods for plasma treated metal silicide layer formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a metal layer on a silicon substrate, exposing the metal layer to a plasma, and thermally treating the silicon substrate and the metal layer to form a metal silicide layer.Type: GrantFiled: August 20, 2008Date of Patent: March 8, 2011Assignee: Spansion LLCInventors: Takayuki Enda, Tatsuya Inoue, Naoki Takeguchi
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Patent number: 7893532Abstract: An external contact material for external contacts of a semiconductor device and a method for producing the same are described. The external contact material includes a lead-free solder material. Provided in the solder material is a filler which forms a plurality of gas pores and/or has plastic particles which are arranged in the volume of the solder material.Type: GrantFiled: September 13, 2006Date of Patent: February 22, 2011Assignee: Infineon Technologies AGInventors: Michael Bauer, Irmgard Escher-Poeppel, Edward Fuergut, Simon Jerebic, Bernd Rakow, Peter Strobel, Holger Woerner
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Semiconductor device having a refractory metal containing film and method for manufacturing the same
Patent number: 7888254Abstract: A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO2 film provided on the silicon substrate, copper films embedded in the SiO2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO2 film, and SiON films covering an upper face of the TiN films.Type: GrantFiled: February 20, 2009Date of Patent: February 15, 2011Assignee: Renesas Electronics CorporationInventors: Toshiyuki Takewaki, Mari Watanabe -
Publication number: 20110006409Abstract: Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds (or alloys) and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit having a drain on the backside of the substrate, a TiNi contact layer contacting the drain on the backside of the substrate, a soldering layer on the contact layer, an oxidation reducing layer on the soldering layer, a solder bump on the soldering layer, and a lead frame attached to the solder bump. The combination of the Ti and Ni materials in the contact layer exhibits many features not found in the Ti and Ni materials alone, such as reduced backside on-resistance, ability to form a silicide with the Si substrate at lower temperatures, reduced wafer warpage, increased ductility for improved elasticity, and good adhesion properties. Other embodiments are described.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Inventors: Michael D. Gruenhagen, James J. Murphy, Suku Kim, Jim Pierce, William S. Beggs, Robert J. Purtell
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Publication number: 20100327451Abstract: An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region.Type: ApplicationFiled: September 8, 2010Publication date: December 30, 2010Inventors: Ling-Chun Chou, Ming-Tsung Chen, Hsi-Hua Liu, Shuen-Cheng Lei, Po-Chao Tsao
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Publication number: 20100283145Abstract: A stack structure with copper bumps on an integrated circuit board is disclosed. The stack structure includes a plurality of insulating layers and a plurality of conductive layers which are stacked alternately. The uppermost conductive layer has copper bumps as copper pillar pins for soldering the chip pins of an integrated circuit chip. Because the copper bumps have a certain height, the distance between the copper bumps and the chip pins is shortened, and therefore the solders needed for soldering may be reduced. Also, the shape of the solders is a long strap instead of spheroid due to the cohesion force between the copper bump surfaces and the solders so that the distance between the solders is scaled down and the gaps between the pins are reduced. Thus, the entire size of the integrated circuit board may also be miniatured.Type: ApplicationFiled: May 5, 2009Publication date: November 11, 2010Inventors: Chien-Wei Chang, Ting-Hao Lin, Yu-Te Lu, Wen-Chun Huang
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Publication number: 20100244266Abstract: The present invention discloses a metallic bonding structure for copper and solder, which applies to connect at least one electronic element. The metallic bonding structure comprises at least one copper-based member and at least one zinc bonding member. The copper-based members are arranged on the electronic element through at least one solder member. The zinc bonding members are arranged between the copper-based members and the solder members. The solder members are tin-based solder bumps.Type: ApplicationFiled: March 27, 2009Publication date: September 30, 2010Inventors: Jenq-Gong Duh, Chi-Yang Yu
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Publication number: 20100244105Abstract: A semiconductor structure having: a semiconductor comprising a indium gallium phosphide and molybdenum metal in Schottky contact with the semiconductor.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Inventor: Kiuchul Hwang
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Patent number: 7804172Abstract: Electrical connections between different materials. An electrical connection system includes electrical components and an electrical connection between the electrical components. The electrical connection includes a functionally graded material. A method of making an electrical connection between different materials includes the steps of: providing an electrical component which includes a material; providing another electrical component which includes another material; and electrically connecting a functionally graded material between the electrical components. An electrical connection system includes an electrical component and a functionally graded material electrically connected to the electrical component. The functionally graded material provides a gradual transition between at least two dissimilar materials.Type: GrantFiled: January 10, 2006Date of Patent: September 28, 2010Assignee: Halliburton Energy Services, Inc.Inventors: Roger L. Schultz, Michael L. Fripp, Haoyue Zhang, Daniel D. Gleitman