Abstract: A method for manufacturing a display device includes the steps of: providing a first display panel including a first indicia and a second indicia; disposing a first window including a third indicia on the first display panel; identifying a position of the first indicia and a position of the third indicia; aligning the first display panel and the first window using the positions of the first and third indicia; coupling the first window and the first display panel to each other; identifying a coupled position defined by positions of the second and third indicia of the first display panel and the first window; correcting a position of a second display panel or a position of a second window based on the coupled position; and coupling the second window and the second display panel to each other.

Abstract: High performance modules for use in System-in-Package (SIP) devices, and methods of manufacture for such modules and SIPs. The modules employ one or more interposer substrates on which high performance components and/or devices are operatively mounted and interconnected.

Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.

Abstract: Embodiments of the present disclosure provide an alignment mark evaluation method and an alignment mark evaluation system. The alignment mark evaluation method includes: setting a process step code of a wafer with an alignment mark to be evaluated as an evaluation code; obtaining a current process step code of the wafer; if it is detected that the current process step code is the evaluation code, switching a step to be executed to an alignment mark evaluation step; and executing the alignment mark evaluation step to evaluate the alignment mark to be evaluated.

Abstract: A chip on film package structure including a flexible film, a patterned metal layer, a chip, a patterned solder resist layer, and a code-included pattern is provided. The flexible film comprises a chip mounting region and a peripheral region surrounding the chip mounting region. The patterned metal layer disposed on the flexible film. The chip mounted on the chip mounting region and electrically connected to the patterned metal layer. The patterned solder resist layer exposing the chip mounting region and covering a part of the patterned metal layer. The code-included pattern disposed on the peripheral region of the flexible film. The code-included pattern comprises a plurality of machine-readable data. A method for reading a code-included pattern on a package structure is also provided.

Abstract: Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.

Abstract: A method of testing a semiconductor package including a plurality of semiconductor chips includes sensing electrical signals respectively output from a plurality of semiconductor chip groups each representing a combination of at least two semiconductor chips among the plurality of semiconductor chips, obtaining amplitudes of electrical signals respectively output from the plurality of semiconductor chips based on the plurality of sensed electrical signals, and outputting a test result for the semiconductor package by using the plurality of obtained electrical signals.

Abstract: Techniques and architecture are disclosed for a system that includes a fuze at a leading end of a projectile body and a fuze setter configured to engage the fuze and to program the same prior to launch. The system, in one example, includes a plurality of electrical contact pads on an exterior surface of a fuze radome housing and a plurality of electrical contact pins on the fuze setter. The electrical contact pads are arranged in a rotationally symmetric pattern that enables an electrical interface to be formed with the electrical contact pins, regardless of the rotational orientation of the fuze. Commutation is performed to rotate signals to the electrical contact pins instead of requiring that the fuze be physically rotated to bring the electrical contact pads into alignment with the electrical contact pins.

Abstract: A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.

Abstract: An apparatus includes a substrate; circuit components disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer includes one or more section labels for representing physical locations of the circuit components within the apparatus.

Abstract: A method of manufacturing a semiconductor device includes: forming a first outer box and a second outer box on a wafer, providing a photoresist layer on the wafer; and by removing a portion of the photoresist layer, forming a photoresist pattern including a first opening and a second opening that are horizontally apart from each other, wherein the first opening defines a first inner box superimposed on the first outer box in a plan view, the second opening defines a second inner box superimposed on the second outer box in the plan view, and a horizontal distance between the first opening and the second opening is about 150 ?m to about 400 ?m.

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Abstract: A method for producing a light-emitting device includes: bonding a plurality of light-emitting elements to a plate-shaped light transmission member all at once with the plurality of light-emitting elements being arranged in a two-dimensional array extending in a first direction and a second direction; capturing an image of the plurality of light-emitting elements bonded to the light transmission member, and forming an alignment mark on the light transmission member based on positions in the image of the plurality of light-emitting elements; and after the forming of the alignment mark, forming a contact member in contact with a corresponding one of the plurality of light-emitting elements with the contact member being positioned with respect to the plurality of light-emitting elements by using the alignment mark.

Abstract: A coordinate measuring system includes a scanning module having a laser line scanner and a projection device. The laser line scanner projects a laser line onto a surface of a workpiece and produces scan data from a reflection of the laser line. The projection device and/or the laser line scanner project three optical markers onto the surface of the workpiece, at least one of the three markers being disposed on the laser line and at least one of the three markers being at a distance from the laser line. The coordinate measuring system includes an optical sensor capturing image data of the three optical markers and an evaluation device determining a position and an orientation of the coordinate system of the laser line scanner in the coordinate system of the optical sensor based on the image data of the optical sensor and the scan data of the laser line scanner.

Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.

Abstract: A workpiece unit includes a wafer, a tape attached to the wafer, and an annular frame to which an outer peripheral edge of the tape is attached and having an opening in a center of the annular frame, and the workpiece unit has the wafer positioned in the opening of the annular frame through the tape. In the workpiece unit, the tape has a color change layer that reversibly changes in color in response to a change in temperature caused by cooling.

Abstract: A production information management system includes a storage device, a search tool, a data processing tool, and an integration tool. The storage device stores production information therein. The data processing tool performs data processing based on input data. Based on processing procedure information indicating a predetermined processing procedure, the integration tool performs a series of processes according to the processing procedure using a plurality of individual tools including the search tool and the data processing tool. The integration tool inputs a search condition based on the processing procedure information to the search tool information and causes the search tool to acquire data meeting the search condition from the production information. The integration tool inputs search result data acquired by the search tool to the data processing tool and causes the data processing tool to perform data processing based on the search result data.

Abstract: Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.

Abstract: This invention provides an integrated circuit chip comprising a plurality of signal processing circuits formed by stepping exposure, a bus formed by one-shot exposure, an arbitration circuit that arbitrates between the plurality of signal processing circuits and the bus, and an input unit that inputs a captured image signal from an image sensor, wherein the plurality of signal processing circuits formed by stepping exposure includes a processing unit that generates a RAW image by carrying out predetermined signal processing on the captured image signal and outputs the RAW image to the exterior, and a generating unit that generates image evaluation information using the bus formed by one-shot exposure and the arbitration circuit, in addition to the generation of the RAW image.

Abstract: Fabrication of an alignment mark in a semiconductor device is simplified. A semiconductor device including a semiconductor substrate, an epitaxial layer, and an alignment mark is provided. The epitaxial layer included in the semiconductor device includes a single-crystalline semiconductor that is epitaxially grown on a surface of the semiconductor substrate included in the semiconductor device. The alignment mark included in the semiconductor device is disposed between the semiconductor substrate and the epitaxial layer.

Abstract: A metal circuit on a polymer composite substrate surface and a method for manufacturing the same are provided. The metal circuit on the polymer composite substrate surface includes a polymer composite layer and a metal circuit layer. The metal circuit layer is formed from a metal piece molded by metal processing, and is integrated onto a surface of the polymer composite layer. The metal circuit layer has one or a plurality of circuit grooves formed therein, the polymer composite layer has one or a plurality of bulges formed therein, and the bulge is deformed and bulged at the corresponding circuit groove.

Abstract: A maintenance tool for semiconductor process equipment and components. Sensor data is evaluated by machine learning tools to determine when to schedule maintenance action.

Abstract: An overlay error measurement structure includes a lower-layer pattern disposed over a substrate, and an upper-layer pattern disposed over the lower-layer pattern and at least partially overlapping with the lower-layer pattern. The lower-layer pattern includes a plurality of first sub-patterns extending in a first direction and being arranged in a second direction crossing the first direction. The upper-layer pattern includes a plurality of second sub-patterns extending in the first direction and being arranged in the second direction. At least one of a pattern pitch and a pattern width of at least one of at least a part of the first sub-patterns and at least a part of the second sub-patterns varies along the second direction.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A processing method for a workpiece includes a cutting step of cutting the workpiece along streets by a cutting blade having a V-shaped tip end, to form V grooves of which shallower parts are wider than deeper parts, and a cleaning step of cleaning a back surface of the workpiece with cleaning water, after the cutting step is carried out.

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

Abstract: A carrier having one or more conductive terminals is provided. A semiconductor die is mounted on the carrier. The semiconductor die is electrically connected to the one or more conductive terminals. The semiconductor die is encapsulated with an electrically insulating mold compound. A verification rule that tests whether inputted information satisfies authentication criteria is created. A first identification feature is formed on a metal structure that is encapsulated by the mold compound. The first identification feature comprises one or more symbols from a first data representation scheme that are covered by the mold compound. The one or more symbols of the first identification feature are selected to convey information that satisfies the authentication criteria of the verification rule.

Abstract: An advanced security method for verifying that integrated circuit patterns being processed into one or more layers provided to a wafer are trusted patterns and that the wafer being used during processing is a trusted wafer is provided. The method includes separate steps of pattern verification and wafer verification. Notably, the method includes first verifying that a pattern printed on a wafer matches a pattern of a trusted reference. Next, a peak and valley profile present at a specific location on a backside surface of the wafer is measured. The method further includes second verify that the measured peak and valley profile matches an original peak and valley profile measured at the same location on the backside surface of the wafer.

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

Abstract: In a general aspect, a for producing a fan-out wafer level package (FOWLP) semiconductor device can include separating a semiconductor wafer into a plurality of semiconductor die and, after separating the semiconductor wafer into the plurality of semiconductor die, increasing spacing between the plurality of semiconductor die. The method can further include encapsulating, in a molding compound, the plurality of semiconductor die and determining respective locations of one or more alignment features disposed within the molding compound. The method can still further include forming, based on the determined respective locations, one or more alignment marks in the molding compound.

Abstract: An integrated circuit includes an array of devices with a logic pattern to implement a physically unclonable function (PUF) for chip authentication. The logic pattern is determined in accordance with processing variations during the manufacturing. The array of devices includes one or more components having a first state and one or more components having a second state. A combination of the first and second states provides the logic pattern.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion, and the first strip portion and the second strip portion are elongated in a first elongated axis and are spaced apart from each other. The method includes forming a layer over the first overlay grating. The layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion.

Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)?2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region. The method includes forming a first layer on the substrate. The first layer has a first hole on the first region and a second hole on the second region. The method includes forming a second layer in the first hole and the second hole. The method includes forming a mask pattern on the second region of the substrate. The method includes polishing the second layer to form a pattern in the first hole and an overlay key pattern in the second hole. A top surface of the overlay key pattern is further from the substrate than a top surface of the pattern in the first hole.

Abstract: An on-wafer calibration device comprises on a substrate at least a first measuring port, at least a first switch element, at least two calibration standards, and a controller unit or a control interface for control of the first switch element. The first switch element is controlled in a manner that it selectively connects a wafer probe tip connectable to the first measuring port to the at least two calibration standards.

Abstract: Testing data is evaluated by machine learning tools to determine whether to include or exclude chips from further testing.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.

Abstract: An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip is a member of a set of semiconductor chips, the set of semiconductor chips comprises a plurality of subsets of semiconductor chips, and the semiconductor chip is a member of only one of the subsets. The plurality of structures of the semiconductor chip includes a set of common structures which is the same for all of the semiconductor chips of the set, and a set of non-common structures, wherein the non-common structures of the semiconductor chip of the subset is different from a non-common circuit of the semiconductor chips in every other subset. At least a first portion of the non-common structures and a first portion of the common structures form a first non-common circuit, wherein the first non-common circuit of the semiconductor chips of each subset is different from a non-common circuit of the semiconductor chips in every other subset.

Abstract: A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.

Abstract: Disclosed herein is a method for encoding an illustration on a target surface, where the illustration may be visible when light is shone on the surface from a light source with a predetermined position. The method may include converting the illustration into a grayscale illustration, specifying the position of the light source; generating a three dimensional surface having a grid of smaller surfaces thereon, where each smaller surface may represent a corresponding pixel of the grayscale illustration. Each smaller surface may be oriented with respect to the light source such that reflected light from each smaller surface has a reflection intensity equal to the light intensity of the corresponding pixel of the greyscale illustration; and making the target surface out of a material using the generated three dimensional surface as a template.

Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.

Abstract: [Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75. The recess 75 has a recess groove 753 outside the die pad 11 in a direction in which the die pad rear surface 112 extends, and the recess groove 753 is closer to the die pad main surface 111 than to the die pad rear surface 112. The heat releasing layer 6 has a junction layer which is in contact with the die pad rear surface 112 and having part thereof filling the recess groove 753.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The first overlay grating has a first strip portion and a second strip portion. The method includes forming a first layer over the first overlay grating. The first layer has a first trench elongated in a second elongated axis, the second elongated axis is substantially perpendicular to the first elongated axis, and the first trench extends across the first strip portion and the second strip portion. The method includes forming a second overlay grating over the first layer. The second overlay grating has a third strip portion and a fourth strip portion. The third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other.

Abstract: An alignment mark searching method is for searching an alignment mark on a base substrate, a first positioning line segment is formed in a dummy region of the base substrate, and a straight line where the first positioning line segment is positioned running through the alignment mark. The method includes: acquiring theoretical coordinates of the alignment mark; moving a detection system view field to a target position with the theoretical coordinates as a target; moving the detection system view field from the target position in a direction perpendicular to the first positioning line segment until the first positioning line segment appears in the detection system view field; and moving the detection system view field from the position of the first positioning line segment in a length direction of the first positioning line segment until the alignment mark appears in the detection system view field. The method achieves an effect that the alignment mark can be simply, conveniently and rapidly searched.

Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.

Abstract: Feature extraction and classification is used for process window monitoring. A classifier, based on combinations of metrics of masked die images and including a set of significant combinations of one or more segment masks, metrics, and wafer images, is capable of detecting a process non-compliance. A process status can be determined using a classifier based on calculated metrics. The classifier may learn from nominal data.

Abstract: A chip part includes a substrate having a first main surface on one side thereof and a second main surface on the other side thereof, a functional device famed at a first main surface side of the substrate, an external terminal formed at the first main surface side of the substrate and electrically connected to the functional device, and a light diffusion reflection structure formed at a second main surface side of the substrate and diffusely reflecting light irradiated toward the second main surface of the substrate.

Abstract: A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Abstract: A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device.

Abstract: An image sensor module that comprises a die, wherein the die comprises light sensors and optics; and wherein the optics comprises luminescent elements that represent die manufacturing information that is indicative of a manufacturing process of the die.