Mixed Assemblies (epo) Patents (Class 257/E25.025)
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Patent number: 11139723Abstract: A rectifier assembly according to an example of the present disclosure includes, among other things, a first housing and a second housing extending along an assembly axis, the first housing surrounding a pair of electrical rings. At least one spring strip includes a first spring strip portion transverse to a second spring strip portion, the second spring strip portion to bias diodes against an inner periphery of the pair of electrical rings. The second housing includes at least one connection terminal for receiving a wire from an exciter rotor, the at least one connection terminal including a screw threaded area which receives a bolt holding the first spring strip portion. A generator and a method of assembling a rectifier assembly are also disclosed.Type: GrantFiled: July 17, 2017Date of Patent: October 5, 2021Assignee: HAMILTON SUNDSTRAND CORPORATIONInventors: Dhaval Patel, Glenn C. Lemmers, Jr., Edward C. Allen, Andrew R. Wilkinson
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Patent number: 10491081Abstract: In the present rectifying apparatus, a circuit board is disposed between a first rectifying element holding portion and a second rectifying element holding portion, and is configured such that only a housing linking portion, a stator winding connecting portion, and a voltage regulator connecting portion protrude from the first rectifying element holding portion and the second rectifying element holding portion when viewed from an axial direction, a plurality of first radially inner fins are formed on a radially inner side of the first rectifying element holding portion, and a plurality of second radially outer fins are formed on a radially outer side of the second rectifying element holding portion.Type: GrantFiled: November 21, 2014Date of Patent: November 26, 2019Assignee: Mitsubishi Electric CorporationInventors: Masao Akiyoshi, Yuzuru Kobayashi
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Patent number: 8426979Abstract: A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring.Type: GrantFiled: July 18, 2011Date of Patent: April 23, 2013Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
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Patent number: 8049319Abstract: This research discloses an ultra wideband system-on-package (SoP). The SoP includes a package body; a first integrated circuit mounted on the package body; a first signal transmission unit connected to the first integrated circuit; a signal via connected to the first signal transmission unit and including a slab line and a trough line; and a second signal transmission unit connected to the signal via. The technology of the present research can transmit ultra broadband signals by minimizing discontinuity of signals appearing during vertical transition that occurs in the course of a signal transmission to/from an external circuit, and a fabrication method thereof.Type: GrantFiled: October 22, 2009Date of Patent: November 1, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: In-Kwon Ju, In-Bok Yom, Ho-Jin Lee
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Patent number: 8035115Abstract: A semiconductor apparatus includes a substrate; and a plurality of semiconductor thin films formed on said substrate, each of said semiconductor thin films having a pn-junction, and electrodes of p-type and n-type for injecting carriers to the pn-junction, wherein said semiconductor thin films are formed so that all or a part of said pn-junctions are connected serially. As different from a semiconductor thin film constituted of a single pn-junction, the light emission with the invented semiconductor apparatus is the summation of the light emission intensities of the entire pn-junctions, so that the light emitting intensity can be increased largely.Type: GrantFiled: May 11, 2006Date of Patent: October 11, 2011Assignee: Oki Data CorporationInventors: Mitsuhiko Ogihara, Takahito Suzuki, Hiroshi Kurokawa, Taishi Kaneto
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Patent number: 8030134Abstract: Stacked semiconductor assemblies in which a first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.Type: GrantFiled: September 28, 2006Date of Patent: October 4, 2011Assignee: Chippac, Inc.Inventors: Hyeog Chan Kwon, Marcos Karnezos
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Patent number: 7986023Abstract: One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.Type: GrantFiled: September 17, 2007Date of Patent: July 26, 2011Assignee: Infineon Technologies AGInventors: Helmut Tews, Hans-Gerd Jetten, Hans-Joachim Barth
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Patent number: 7948078Abstract: A semiconductor device has a package structure provided with leads that are external connection terminals. A base substance is an island, and at least the surface thereof is formed of a conductive material. A semiconductor substrate is mounted on the surface of the base substance, and a ground potential is supplied from the surface of the base substance. A shunt capacitor is provided with an electrode pair of a first electrode and a second electrode formed in parallel, and mounted with the first electrode being electrically connected to the surface of the base substance. An internal bonding wire connects a pad provided on the semiconductor substrate for external connection, to the second electrode of the shunt capacitor. The lead is the external connection terminal of the semiconductor device. An external bonding wire connects the lead to the second electrode of the shunt capacitor.Type: GrantFiled: July 24, 2007Date of Patent: May 24, 2011Assignee: Rohm Co., Ltd.Inventor: Noriaki Hiraga
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Patent number: 7598535Abstract: An LED assembly includes a packaged LED module (30) and a heat dissipation device (50). The LED module includes at least an LED die therein and a plurality of conductive pins (32, 34) extending downwardly from a bottom portion thereof. The heat dissipation device is thermally and electrically connected with the at least an LED die. The heat dissipation device defines at least a mounting hole (542) therein. At least one of the conductive pins is fittingly received in the at least a mounting hole and thermally and electrically connects with the heat dissipation device.Type: GrantFiled: July 20, 2006Date of Patent: October 6, 2009Assignee: Foxconn Technology Co., Ltd.Inventors: Tseng-Hsiang Hu, Yeu-Lih Lin, Li-Kuang Tan
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Patent number: 7256431Abstract: An insulating substrate includes a metal base as a base member, an insulating layer which is a room temperature, aerosol deposited shock solidification film formed on the metal base, and a circuit pattern which is a cold sprayed thermal spray coating formed on the insulating layer. A semiconductor device incorporates the insulating substrate, and thereby has improved heat radiation characteristics.Type: GrantFiled: November 22, 2005Date of Patent: August 14, 2007Assignee: Fuji Electric Holdings Co., Ltd.Inventor: Kenji Okamoto