Abstract: A semiconductor module, including a metal-oxide-semiconductor field effect transistor (MOSFET) made of a SiC semiconductor material, and an insulated gate bipolar transistor (IGBT) that is made of a Si semiconductor material and is connected in parallel with the MOSFET. The MOSFET having a body diode. The IGBT is a reverse conductive-IGBT (RC-IGBT), and includes a free wheeling diode. A forward voltage of the free wheeling diode is so set that a current in the body diode of the MOSFET, which is connected in parallel with the RC-IGBT, is equal to or below a current value that causes lattice defects to grow in the MOSFET.

Abstract: Forming aluminum circuit layers forming an aluminum circuit layers on one surface of a ceramic substrate and forming copper circuit layers are included. The copper circuit layers are formed by laminating copper boards for the circuit layers on the respective aluminum circuit layers, arranging the laminate between a pair of support boards having a convex curved surface at least on one surface so as to face to each other, moving the support boards in a facing direction to press the laminate in a lamination direction, and heating in this pressing state so that the copper boards for the circuit layers are bonded on the aluminum circuit layers respectively by solid phase diffusion. In the step of forming the copper circuit layers, the support boards are arranged so that either one of the convex curved surface is in contact with the adjacent copper boards for the circuit layers in the laminate.

Abstract: A power converter includes an integrated multi-layer cooling structure. The power converter includes a plurality of printed circuit boards (PCBs) stacked together in a generally vertical arrangement. A liquid cooling mechanism is attached to a lower-most PCB, and high loss circuitry components are attached to an opposite side of the lower-most PCB. Low loss circuitry components are attached to further PCBs. Magnetic components may be attached to the further PCBs. The high loss components are actively cooled by the liquid cooling mechanism and the low loss components and magnetic components are passively cooled. The liquid cooling mechanism may be a cold plate heatsink. The power converter may include intermediate PCBs disposed between the upper-most PCB and the lower-most PCB, with low loss circuitry components attached to the intermediate PCBs.

Abstract: The present disclosure provides a dual mode antenna, comprising: a first conductive piece; and a second conductive piece, configured to electromagnetically couple with the first conductive piece through a dielectric at a second frequency to operate as a loop antenna with the first conductive piece and configured to operate independently of the first conductive piece at a first frequency to operate as a monopole antenna. The dual mode antenna can be included in an antenna array as one of a plurality of dual mode antennas coupled to a routing substrate or a reference dual mode antenna coupled to the routing substrate along with a plurality of single mode antennas coupled to the routing substrate; wherein each antenna of the plurality of dual mode antennas, the reference dual mode antenna, and the plurality of single mode antennas is arranged evenly relative to a first neighboring antenna and a second neighboring antenna.

Abstract: The present embodiment relates to an electronic component assembly comprising: a housing; a heating element disposed inside the housing; a substrate disposed on the heating element; and a spacer disposed between the heating element and the substrate, wherein the substrate has a first hole coupled to the spacer, the heating element includes a first body having a second hole formed therethrough, and a connection part connected to the substrate, and the spacer includes a first protrusion coupled to the first hole, a second protrusion coupled to the second hole, and a second body disposed between the first protrusion and the second protrusion.

Abstract: A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

Abstract: A power conversion module and method of forming the same includes a motherboard having a first surface and a second surface that opposes the first surface. The motherboard includes a first trace that electrically couples a decoupling capacitor mounted on the motherboard to a first pad on the first surface of the motherboard and an output node of a power conversion module. The motherboard includes a via extending through the motherboard that electrically couples a second pad on the first surface of the motherboard and a third pad on the second surface of the motherboard to the output node and a second trace that electrically couples a fourth pad on the second surface of the motherboard and the decoupling capacitor. The power module includes a first daughterboard mounted on the first surface of the motherboard and a second daughterboard mounted on the second surface of the motherboard.

Abstract: A fan-out type semiconductor package includes: a frame including a cavity and a middle redistribution layer (RDL) structure at least partially surrounding the cavity; a semiconductor chip in the cavity; a lower RDL structure on the frame and electrically connected with the semiconductor chip and the middle RDL structure; an upper RDL structure on the frame and electrically connected with the middle RDL structure; an upper shielding pattern in the upper RDL structure to shield the semiconductor chip from electromagnetic interference (EMI); a lower shielding pattern in the lower RDL structure to shield the semiconductor chip from the EMI; and a side shielding pattern in the middle RDL structure to shield the semiconductor chip from the EMI. The upper shielding pattern and the lower shielding pattern have a thickness of no less than about 5 ?m, and the side shielding pattern has a width of no less than about 5 ?m.

Abstract: A semiconductor device has a substrate, a first circuit, a first inductor, a second circuit and a second inductor IND2. The substrate includes a first region and a second region, which are regions different from each other. The first circuit is formed on the first region. The first inductor is electrically connected with the first circuit. The second circuit is formed on the second regions. The second inductor is electrically connected with the second circuit and formed to face the first inductor. A penetrating portion is formed in the substrate. The penetrating portion is formed such that the penetrating portion surrounds one or both of the first circuit and the second circuit in plan view.

Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

Abstract: A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

Abstract: An integrated circuit package comprising one or more electronic component(s); and one or more substrate(s), including a first substrate and a second substrate, wherein said first substrate including a first cavity on a first surface of said first substrate and a second cavity on a second surface of said first substrate, said second substrate includes a third cavity on a first surface of said second substrate and a fourth cavity on a second surface of said second substrate, said first substrate and said second substrate are stacked and coupled, and said one or more electronic component(s) is/are disposed inside said first cavity of first substrate and said fourth cavity of second substrate.

Abstract: A common mode choke coil includes a core, and first and second coils opposed to each other and wound on the core. The core can have a square shape, or an elongated shape having a long axis and a short axis when viewed in a direction along a central axis of the core. Each of the first and second coils is a single-layer coil. An area of a cross-section of the core taken perpendicular to a circumferential direction of the core is constant in the circumferential direction of the core. The cross-section of the core has a quadrilateral shape.

Abstract: A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

Abstract: A package comprises a molding and a conductive terminal in contact with the molding and having a first surface exposed to a first surface of the molding. The conductive terminal includes a cavity having a first portion extending along at least half of the first surface of the conductive terminal and a second portion extending along less than half of the first surface of the conductive terminal.

Abstract: Provided is an electronic component mounting structure and method for mounting electronic components on the side of a printed circuit board by means of simple fabrication and enlarging the surface area for mounting electronic components. A cut face of a conductive plating layer, which is obtained by cutting along a via in which a conductive plating layer covering an inner wall face of a via hole is electrically connected to a conductive pattern layer of the printed circuit board, is exposed at a cut end face and used as a land pattern which is solder-connected to a mount connecting portion of the electronic component. The end face at which the land pattern is exposed is a surface parallel to the side of the printed circuit board, and therefore electronic components can be mounted on the end face parallel to the side.

Abstract: In one embodiment, a device includes a flexible substrate, a touch sensor made of flexible conductive material disposed on the flexible substrate, and conductive tracks made of flexible conductive material disposed on the flexible substrate. The device also includes an electrical component bonded to the conductive tracks. The conductive tracks electrically couple the electrical component to the touch sensor.

Abstract: A system-in-a-package (SIP) has a semiconductor chip embedded in a dielectric substrate. An inductor is on a top surface of a substrate and is connected to the semiconductor chip. A thin film capacitor may be placed between the inductor and the dielectric substrate. A second thin film capacitor may be placed on the top surface of the semiconductor chip, or be embedded in the dielectric substrate with a thermal pad on a bottom surface of the substrate which is connected to the second thin film capacitor to facilitate heat dissipation.

Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.

Abstract: A substrate for mounting a light-emitting element, containing a substrate main body having a mounting surface on which a light-emitting element is to be mounted, a reflection layer formed on a part of the mounting surface of the substrate main body and containing silver to reflect light emitted from the light-emitting element, and a vitreous insulating layer formed on the reflection layer, wherein the vitreous insulating layer contains a glass containing SiO2, at least one of Al2O3 and B2O3, and at least one member selected from Li2O, Na2O and K2O, wherein (Li2O+Na2O+K2O)—Al2O3 is from ?20 to 1.5% and Si02+3×Al2O3 is at most 90% calculated using the mol % of each of said SiO2, Al2O3 B2O3, Li2O, Na2O and K2O in said glass.

Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.

Abstract: A method of manufacturing a hybrid integrated circuit device of the present invention includes the steps of preparing a lead frame which constituted by units each having a plurality of leads, and fixing a circuit substrate on each unit of the lead frame by fixing pads which are formed on the surface of the circuit substrate to the leads, where a space between a first pad which is formed at an end edge of the circuit substrate and a second pad which is adjacent to the first pad is set narrower than a space between the pads themselves.

Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

Abstract: An integrated circuit module package includes a lead frame having a recessed area. A semiconductor die containing active electrical components is attached to the recessed area of the lead frame. An integrated passive device containing passive electrical components is vertically stacked with, and electrically coupled to, the semiconductor die. An optional heat sink is attached to the integrated passive device. The integrated passive device is connected to the lead frame by conductors to electrically couple the integrated passive device and the semiconductor die to circuitry external to the integrated circuit module package. A cap is then attached to the heat sink or the integrated passive device to protect the semiconductor die and the integrated passive device. The integrated circuit module package dissipates heat from the semiconductor die through the lead frame, and dissipates heat from the integrated passive device through the cap and optional heat sink.

Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.

Abstract: A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the second major surface side. The chip part has a projection electrode on the bottom surface. The insulating resin layer holds the chip part such that the bottom and side surfaces of the chip part are in contact with the insulating resin layer, and the top surface of the chip part is exposed on the insulating layer on the first major surface side. The projection electrode of the chip part is connected with the first wiring layer.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: The power semiconductor module (1) has a heat-conducting base plate (11) on which at least three substrates (2, 3, 4, 5, 6, 7) are placed, each substrate supporting at least one power semiconductor component (8, 9) that gives off heat generated during operation. In order to optimize a power semiconductor module of this type with regard to mechanical load and heat dissipation, the substrates (2, 3, 4, 5, 6, 7) are placed on the base plate (11) while being arranged in a single row (12), and pressing devices (15, 16), which are situated close to the substrate, are provided on both longitudinal sides (11a, 11b) of the base plate (11) while being arranged parallel to the row (12). The base plate can be pressed against a cooling surface by the pressing devices.

Abstract: A RF system which includes a silicon substrate formed with at least one via-hole filled with conductive material so that both sides of the silicon substrate are electrically connected with one another; at least one flat device formed on one side of the silicon substrate; and at least one RF MEMS device formed on the other side of the silicon substrate.

Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

Abstract: Semiconductor packages that contain multiple dies and methods for making such packages are described. The semiconductor packages contain a leadframe with multiple dies and also contain a single premolded clip that connects the dies. The premolded clip connects the solderable pads of the source die and gate die to the source and gate of the leadframe via standoffs. The solderable pads on the dies and on the standoffs provide a substantially planar surface to which the premolded clip is attached. Such a configuration increases the cross-sectional area of the interconnection when compared to wirebonded connections, thereby improving the electrical (RDSon) and the thermal performance of the semiconductor package. Such a configuration also lowers costs relative to similar semiconductor packages that use wirebonded connections. Other embodiments are described.

Abstract: An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip.

Abstract: A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n?2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.

Abstract: An integrated circuit package system comprising: providing a package substrate; attaching a base package having a portion of the base package substantially exposed over the package substrate; forming a cavity through the package substrate to the base package; and attaching a device partially in the cavity and connected to the portion of the base package substantially exposed.

Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

Abstract: A method for creating an improved signal light is disclosed. For example, the improved signal light includes a housing, one or more first type of light emitting diodes (LEDs) emitting a light energy having a first dominant wavelength deployed in the housing, one or more second type of LEDs emitting a light energy having a second dominant wavelength deployed in the housing, a filter and a mixer. The filter may filter the light energy of the one or more second type of LEDs such that only a third dominant wavelength passes from the one or more second type of LEDs. The mixer may mix the light energy having the first dominant wavelength and the filtered light energy having the third dominant wavelength to form a light energy having a desired fourth dominant wavelength.

Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

Abstract: A package includes a carrier, a first chip, a first dielectric layer and at least one first connecting part. The carrier has a first surface and a second surface, and at least one first pad is disposed on the second surface. The first chip is disposed on the first surface. The first dielectric layer is disposed on the first surface and covers the first chip. The first connecting part is disposed in the first dielectric layer and disposed around an edge of the first chip to electrically connect the first chip with the first pad. A package module of the package is also disclosed.

Abstract: Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction or heat removal for semiconductor devices and the methods for the stacking thereof are disclosed.

Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.

Abstract: The power semiconductor apparatus includes a resin package made up of a power semiconductor element and a control semiconductor element which are mounted on a main front surface of a lead frame and sealed with mold resin, a power terminal led out of the resin package and electrically connected to the power semiconductor element, a control terminal led out of the resin package and electrically connected to the control semiconductor element and a cylindrical case which is formed in a manner separable from the resin package and encloses the resin package, wherein the power terminal and the control terminal are led out of lead insertion slots formed in the case, and a part of the power terminal which is led out of the case is bent along an end face of the case.

Abstract: A circuit device includes a ceramic substrate, an Al wiring layer provided on the ceramic substrate, and a semiconductor device and a bus bar which are electrically connected to the wiring layer. On part of the wiring layer, a Ni layer is plated. Thus a coated region in which the wiring layer is coated with nickel having solder wetability superior to aluminum and an exposing region in which the wiring layer is exposed as viewed from above the ceramic substrate are provided. The semiconductor device is connected onto the Ni layer within the coated region through solder. The bus bar is ultrasonically bonded to the wiring layer within the exposing region as viewed from above the ceramic substrate. Thus, the circuit device including the semiconductor device and the bus bar that are bonded to the ceramic substrate by sufficient bonding strength and its manufacturing method are provided.

Abstract: A semiconductor device including a first semiconductor element mounted on a first surface of second semiconductor element, wherein solder balls are formed on the first surface of the second semiconductor element such that the first surface includes an area without solder balls. At least one first semiconductor element is mounted to the second semiconductor element at the area of the first surface without solder balls. The at least one first semiconductor element may be mounted to the second semiconductor element using solder joints.

Abstract: An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip.

Abstract: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part piercing the support body and the second substrate. The first substrate includes a first dielectric layer and a wiring layer, a plurality of first electrodes connected to the semiconductor chip which first electrodes are provided on a first surface of the first substrate exposed to an inside of the opening part, and the second substrate includes a second dielectric layer made of a material substantially the same as the first dielectric layer.

Abstract: The specification describes flip bonded dual substrate inductors wherein a portion of the inductor is constructed on a base IPD substrate, a mating portion of the inductor is constructed on a cover (second) substrate. The cover substrate is then flip bonded to the base substrate, thus mating the two portions of the inductor. Using this approach, a two level inductor can be constructed without using a multilevel substrate. Using two two-level substrates yields a four-level flip bonded dual substrate inductor.

Abstract: A multi-chip module is provided which allows memory space extension to improve function and performance. A first semiconductor chip is mounted on a mounting substrate, and a first semiconductor memory chip is mounted over the first semiconductor chip. A second semiconductor memory chip having the same circuitry and the same memory capacity as the first semiconductor memory chip is mounted on a spacer formed on the first memory chip in the same direction as the first semiconductor memory chip. An electrode is independently formed corresponding to a bonding pad to which a selective signal of the first semiconductor memory chip and the second semiconductor memory chip is supplied. A plurality of electrodes are formed in common corresponding to a plurality of bonding pads to which the same signal is respectively supplied except for the selective signal.

Abstract: Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the substrate. The face of the die is aligned with at least a portion of the component layer, and terminals of the die are connected to the substrate.

Abstract: A flip chip stacked package mainly comprises a carrier, a lower chip, an upper chip, a plurality of bumps, a plurality of bonding wires and a supporter. The supporter is attached to the lower surface of the carrier via an adhesive and covers the opening of the carrier. Thus, the lower chip can be disposed in the opening. In addition, the lower chip is electrically flip-chip bonded to the upper chip via the bumps and electrically connected to the carrier via the bonding wires. Accordingly, the heat generated from the lower chip can be transmitted to outside via the supporter. Furthermore, the upper chip is directly exposed to outside so that the capability of the heat dissipation will be enhanced.

Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.