Abstract: Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.

Abstract: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).

Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

Abstract: A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film is formed on its surface. A gate oxide film for a non-volatile memory is formed on a P substrate between N type diffusion layers. The floating gate is formed on the inter-layer silicon oxide film, the field oxide film, and the gate oxide film for the non-volatile memory. Since a large coupling ratio between the control gate and the floating gate is available on the field oxide film, memory rewriting requires only a low voltage. Further, since the control gate is formed by a poly silicon film, both a positive voltage and a negative voltage can be applied to the control gate.

Abstract: A semiconductor device manufacturing method has forming a gate insulation film on a silicon substrate having an nMOS transistor region and a pMOS transistor region, forming a first metal film on the gate insulation film and thereby forming a gate electrode of the nMOS transistor, removing the first metal film in the pMOS transistor region, forming a silicon film on the first metal film in the nMOS transistor region and on the gate insulation film in the pMOS transistor region, forming a second metal film having a work function higher than that of the first metal film on the silicon film and causing reaction between the second metal film and the silicon film and thereby forming a metal silicon compound film which serves as a gate electrode of the pMOS transistor.

Abstract: Provided is an inverter having a new structure capable of easily controlling a threshold voltage according to position in fabricating an inverter circuit on a plastic substrate using an organic semiconductor. A driver transistor is formed with a dual-gate structure and a positive bias voltage is applied to the top gate of the driver transistor so that a body effect appears in the organic semiconductor. Accordingly, the threshold voltage is shifted to a negative zone due to positive potential applied to the top gate of the driver transistor so that the driver transistor acts as an enhancement type transistor. A dual-gate organic structure may be applied to a load transistor rather than the driver transistor, or a p-type dual-gate organic transistor structure may be applied to both the driver transistor and the load transistor.

Abstract: One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of LOCOS regions may be formed on opposite sides of a PFET gate and its corresponding channel, or one or more LOCOS regions may more fully surround, or even completely surround, the PFET channel. In addition, one or more slits may be formed in the LOCOS regions as appropriate to reduce or even completely neutralize the compressive strain in certain directions that would otherwise be applied without the slits. These techniques may be used in silicon-on-insulator (SOI) wafers with or without hybrid orientation technology (HOT) regions.

Abstract: The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.

Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.

Abstract: Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.

Abstract: The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a masking layer over a semiconductor substrate in a first active region and a second active region of a semiconductor device, patterning the masking layer to expose the semiconductor substrate in the first active region, and subjecting exposed portions of the semiconductor substrate to a nitrogen containing plasma, thereby forming a first layer of gate dielectric material over the semiconductor substrate in the first active region.

Abstract: A semiconductor device includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistor of the first conductivity type includes a first gate portion formed on a first region of a semiconductor substrate, a first sidewall formed on each side face of the first gate portion, a first protecting film formed between the first sidewall and the first gate portion, and an extension diffusion layer of the first conductivity type. The transistor of the second conductivity type includes a second gate portion formed on a second region of the semiconductor substrate, a second sidewall formed on each side face of the second gate portion, a second protecting film having an L-shaped cross-section and formed between the second sidewall and the second gate portion and between the second sidewall and the semiconductor substrate, and an extension diffusion layer of the second conductivity type.

Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon germanium layer and a N-channel transistor and a P-channel transistor over the silicon germanium layer. A beta ratio of the N-channel transistor to the P-channel transistor is about 1.8 to about 2.2. A semiconductor device is also disclosed.

Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se

Abstract: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate and the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.

Abstract: A semiconductor device, including a transistor having low threshold voltage and high breakdown voltage, includes a first gate electrode, a second gate electrode, and a third gate electrode arranged on a predetermined first, second, and third region of a semiconductor substrate, respectively, a first gate insulating layer, a second gate insulating layer, and a third gate insulating layer, which are interposed between the first, second and third gate electrode and the semiconductor substrate, respectively, and first, second, and third junction regions arranged in the first, second, and third region of the semiconductor substrate, respectively, on both sides of the first, second and third gate electrode, respectively, wherein a thickness of the first gate insulating layer is greater than a thickness of either of the second or third gate insulating layers, and wherein a structure of the first junction region and a structure of the third junction region are the same.

Abstract: In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

Abstract: A drain diffusion layer 11b includes a low impurity concentration region 5a and a high impurity concentration region 5b, and the low impurity concentration region 5a is located on the channel region side. An impurity layer 7 having an opposite conductivity type to the drain diffusion layer 11b is formed in the channel region, at a position away from the low impurity concentration region 5a by a distance T. Alternatively, the low impurity concentration region 5a and the impurity layer 7 are located so as to contact each other. Still alternatively, a border impurity layer is provided between the low impurity concentration region 5a and the impurity layer 7. Thus, a semiconductor device including a high voltage transistor capable of suppressing the reduction of the electric current driving capability and performing stable driving, and a method for fabricating the same, can be provided.

Abstract: A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device formed therein and a volatile memory device having a volatile memory device formed therein.

Abstract: A method for forming multiple gate insulators on a strained semiconductor heterostructure, including the steps of oxidation and deposition.

Abstract: A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a gate stack of the n-type transistor and a gate stack of the p-type transistor, which each have spacers which are surrounded with oxide. The method further involves etching a portion of the polysilicon from a gate of the p-type field effect transistor, depositing a low resistance material (e.g., Co, Ni, Ti, or other similar metals) on the n-type field effect transistor and the p-type field effect transistor, and heating the integrated circuit such that the deposited material reacts with the polysilicon of the n-type transistor and the polysilicon of the p-type transistor to form silicide.

Abstract: A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor has: a first gate insulating film containing an oxide including an element selected from the group consisting of group IV metals and Lanthanoid metals, and further containing a compound of the element and a group III element; a first gate electrode provided on the first gate insulating film; and n-type source and drain regions formed on both sides of the first gate electrode.

Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 ? (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.

Abstract: A p-channel MOSFET (1) includes a semiconductor substrate (2), an epitaxial region (3), a second diffusion region (6), and a drain region. The epitaxial region (3) is formed on the upper surface of the semiconductor substrate (2). The second diffusion region (6) is formed in a predetermined upper surface area of the epitaxial region (3). The second diffusion region (6) has a central portion (6a) and a peripheral portion (6b). The central portion (6a) is formed substantially at the center of the epitaxial region (3) and formed thicker than the peripheral portion (6b). The peripheral portion (6b) is formed in an annular shape so as to surround the central portion (6a). The drain region (7) is formed in an upper surface area of the central portion (6a) of the second diffusion region (6).

Abstract: A method (200) of forming an isolation structure is disclosed, and includes forming a patterned isolation hard mask layer (206, 212) having an isolation opening associated therewith over a semiconductor body. An implant into the isolation opening is then performed (214), followed by forming an isolation trench (216) in the semiconductor body associated with the isolation opening. The isolation trench is then filled with a dielectric material (218).

Abstract: The present invention provides a method of integrating at least one high voltage metal oxide semiconductor device and at least one Submicron metal oxide semiconductor device on a substrate. The method comprises: providing the substrate, forming a plurality of shallow trenches having different depths on a surface of the substrate, and forming a plurality of silicon oxide layers filling up the shallow trenches, and a top of each of the silicon oxide layers being in the shape of a mushroom.