Including Diode Only (epo) Patents (Class 257/E27.073)
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Patent number: 11557532Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.Type: GrantFiled: August 31, 2020Date of Patent: January 17, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Pen Guo, Carlos H. Diaz, Jean-Pierre Colinge, Yi-Hsiung Lin
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Patent number: 11380380Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.Type: GrantFiled: November 3, 2020Date of Patent: July 5, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti, Guiseppe Scardino
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Patent number: 10510953Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.Type: GrantFiled: April 2, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
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Patent number: 10164002Abstract: A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers.Type: GrantFiled: February 16, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wan-Te Chen, Chung-Hui Chen, Chii-Ping Chen, Chung-Yi Lin, Wen-Sheh Huang
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Patent number: 10102917Abstract: A multi-bit-per-cell three-dimensional read-only memory (3D-OTPMB) comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.Type: GrantFiled: April 14, 2017Date of Patent: October 16, 2018Assignees: ChengDu HaiCun IP Technology LLCInventor: Guobiao Zhang
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Patent number: 9941332Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor overlaying the second transistor or underneath the first transistor, where the second memory cell overlays the first memory cell, and where the first memory cell and the second memory cell have both been processed following a lithography step and accordingly are precisely aligned, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.Type: GrantFiled: January 19, 2017Date of Patent: April 10, 2018Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Zeev Wurman
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Patent number: 9933974Abstract: A method of operating a data storage device includes: receiving a single wipe device initialization command from a host, and in response to the wipe device initialization command, executing a wipe device initialization operation that during a single time period initializes the entirety of a mapping table defining logical partitions dividing memory space provided by a physical region of the data storage device.Type: GrantFiled: November 4, 2014Date of Patent: April 3, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Il Su Han, Keun Soo Jo, Hee Chang Cho
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Patent number: 9502516Abstract: Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.Type: GrantFiled: April 8, 2014Date of Patent: November 22, 2016Assignee: Micron Technology, Inc.Inventors: Jasper S. Gibbons, Darren V. Young, Kunal R. Parekh, Casey Smith
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Patent number: 9466566Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.Type: GrantFiled: February 10, 2015Date of Patent: October 11, 2016Assignee: Macronix International Co., Ltd.Inventor: Hsiang-Lan Lung
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Patent number: 8716745Abstract: A diode is defined on a die. The diode includes a substrate of P conductivity having an upper surface and a lower surface, the substrate having first and second ends corresponding to first and second edges of the die. An anode contacts the lower surface of the substrate. A layer of N conductivity is provided on the upper surface of the substrate, the layer having an upper surface and a lower surface. A doped region of N conductivity is formed at an upper portion of the layer. A cathode contacts the doped region. A passivation layer is provided on the upper surface of the layer and proximate to the cathode.Type: GrantFiled: May 11, 2006Date of Patent: May 6, 2014Assignee: IXYS CorporationInventor: Subhas Chandra Bose Jayappa Veeramma
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Patent number: 8633567Abstract: A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. Numerous other aspects are provided.Type: GrantFiled: December 5, 2012Date of Patent: January 21, 2014Assignee: SanDisk 3D LLCInventor: Scott Brad Herner
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Patent number: 8581242Abstract: The present invention relates to an apparatus combining bypass diode and wire. According to the present invention, the bypass diode can connect with the wire directly. It is not necessary to reserve an extra region on the substrate of the solar cell as the wire soldering area. Thereby, the required area of the ceramic substrate is reduced, and hence lowering the manufacturing cost of the solar cell substantially.Type: GrantFiled: February 21, 2012Date of Patent: November 12, 2013Assignee: Atomic Energy Council—Institute of Nuclear Energy ResearchInventors: Yueh-Mu Lee, Zun-Hao Shih, Hwen-Fen Hong
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Patent number: 8468692Abstract: A variable resistance memory device has memory cells that are operated by Joule's heat and which are highly thermally efficient. Conductive patterns are formed on a substrate; sacrificial patterns exposing a portion of the top surface of each of the conductive patterns are formed on the conductive patterns, lower electrodes are formed by etching upper portions of the conductive patterns using the sacrificial patterns as an etching mask, then mold patterns are formed on the lower electrodes and cover exposed sidewall surfaces of the sacrificial patterns, and then the sacrificial patterns are replaced with variable resistance patterns.Type: GrantFiled: October 4, 2011Date of Patent: June 25, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Byeung Chul Kim
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Patent number: 8450771Abstract: A semiconductor device comprising a plurality of regions of semiconductor material forming a junction at an interface there-between, the junction including a depletion region having a width which varies spatially in at least one direction along the depletion region. Without limitation, the spatial variation in depletion region width is provided by ionised dopants having a concentration which varies spatially along said at least one direction. Alternatively, or in addition, the spatial variation in depletion region width is achieved by varying the thickness of the region(s) of semiconductor spatially along said at least one direction, for example by creating a plurality of cells within said region(s) devoid of said semiconductor material. A method of fabricating a semiconductor device comprising the step of varying the width of the depletion region spatially there-within in at least one direction along the depletion region.Type: GrantFiled: December 17, 2009Date of Patent: May 28, 2013Assignees: Qinetiq Limited, The Secretary of State for Business Innovation and Skills in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Nothern IrelandInventors: Timothy Ashley, Geoffrey Richard Nash
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Patent number: 8334571Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.Type: GrantFiled: March 25, 2010Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 8330250Abstract: A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided.Type: GrantFiled: September 11, 2011Date of Patent: December 11, 2012Assignee: SanDisk 3D LLCInventor: Scott Brad Herner
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Patent number: 8304856Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.Type: GrantFiled: September 13, 2010Date of Patent: November 6, 2012Assignees: Sanyo Semiconductor Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLCInventors: Keiji Mita, Yasuhiro Tamada, Masao Takahashi, Takao Maruyama
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Patent number: 8283751Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.Type: GrantFiled: June 16, 2008Date of Patent: October 9, 2012Assignee: Sidense Corp.Inventor: Wlodek Kurjanowicz
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Patent number: 8203183Abstract: The present invention relates to an electrostatic discharge diode. The electrostatic discharge diode according to exemplary embodiment of the present invention includes: an N-type well formed on a substrate; an n? region formed on the N-type well; a plurality of p? regions penetrated and formed in the n? region; a plurality of n+ regions penetrated and formed in a first layer in which the n? region and a plurality of the p? regions are formed; a plurality of n+ regions penetrated and formed in a first layer in which the n? region and a plurality of the p? regions are formed; and a plurality of p+ regions penetrated and formed in the first layer, wherein a first n+ region among a plurality of the n+ regions and a first p+ region corresponding to the first n+ region are penetrated and formed in each other region of the corresponding first p? region among a plurality of the p? regions.Type: GrantFiled: September 10, 2009Date of Patent: June 19, 2012Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Jun-Hyeong Ryu, Taeg-Hyun Kang, Moon-Ho Kim
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Patent number: 8178972Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.Type: GrantFiled: November 17, 2010Date of Patent: May 15, 2012Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Naoki Yutani
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Patent number: 8129708Abstract: A highly integrated phase change memory device and a method for manufacturing the same is disclosed. The highly integrated phase change memory device includes a semiconductor substrate having a cell area and a peripheral area with impurity regions formed in the cell area and extending in parallel to each other in a first direction to form a striped pattern. A gate electrode is formed in the peripheral area and dummy gate electrodes are formed in the cell area and extending in a second direction perpendicular to the first direction of the impurity regions. An interlayer dielectric layer pattern exposes portions of the cell area and the peripheral area and a PN diode is formed in a space defined by a pair of dummy gate electrodes and a pair of interlayer dielectric layer patterns.Type: GrantFiled: December 29, 2008Date of Patent: March 6, 2012Assignee: Hynix Semiconductor Inc.Inventors: Ki Sung Kwon, Jun Hyung Park
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Patent number: 8089137Abstract: A memory device includes a diode driver and a data storage element, such as an element comprising phase change memory material, and in which the diode driver comprises a silicide element on a silicon substrate with a single crystal silicon node on the silicide element. The silicide element separates the single crystal silicon node from the underlying silicon substrate, preventing the flow of carriers from the single crystal silicon node into the substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node acts as one terminal of a diode, and a second semiconductor node is formed on top of it, acting as the other terminal of the diode.Type: GrantFiled: January 7, 2009Date of Patent: January 3, 2012Assignee: Macronix International Co., Ltd.Inventors: Hsiang-Lan Lung, Erh-Kun Lai
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Publication number: 20110285459Abstract: A semiconductor device includes a power semiconductor array including a first power semiconductor located on one end of the power semiconductor array, a second power semiconductor located on the other end and a third power semiconductor located between the first and second power semiconductors and a diode array including a first diode located on one end of the diode array, a second diode located on the other end and a third diode located between the first and second diodes. A resistance value between an emitter electrode and a collector electrode in ON state is higher at the third power semiconductor than at the first and second power semiconductors. Upon application of a voltage of not less than a rising voltage, the third diode has a higher resistance value than resistance values of the first diode and the second diode upon application of a voltage not less than a rising voltage.Type: ApplicationFiled: February 24, 2011Publication date: November 24, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Hitoshi UEMURA
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Patent number: 8049223Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.Type: GrantFiled: May 25, 2008Date of Patent: November 1, 2011Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Hidekatsu Onose
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Patent number: 8018024Abstract: A method is described for forming a nonvolatile one-time-programmable memory cell having reduced programming voltage. A contiguous p-i-n diode is paired with a dielectric rupture antifuse formed of a high-dielectric-constant material, having a dielectric constant greater than about 8. In preferred embodiments, the high-dielectric-constant material is formed by atomic layer deposition. The diode is preferably formed of deposited low-defect semiconductor material, crystallized in contact with a silicide. A monolithic three dimensional memory array of such cells can be formed in stacked memory levels above the wafer substrate.Type: GrantFiled: November 15, 2006Date of Patent: September 13, 2011Assignee: SanDisk 3D LLCInventor: S. Brad Herner
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Patent number: 8004033Abstract: Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.Type: GrantFiled: June 3, 2009Date of Patent: August 23, 2011Assignee: SanDisk 3D LLCInventors: S. Brad Herner, Maitreyee Mahajani
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Patent number: 7998788Abstract: Techniques for combining nanotechnology with photovoltaics are provided. In one aspect, a method of forming a photovoltaic device is provided comprising the following steps. A plurality of nanowires are formed on a substrate, wherein the plurality of nanowires attached to the substrate comprises a nanowire forest. In the presence of a first doping agent and a first volatile precursor, a first doped semiconductor layer is conformally deposited over the nanowire forest. In the presence of a second doping agent and a second volatile precursor, a second doped semiconductor layer is conformally deposited over the first doped layer. The first doping agent comprises one of an n-type doping agent and a p-type doping agent and the second doping agent comprises a different one of the n-type doping agent and the p-type doping agent from the first doping agent. A transparent electrode layer is deposited over the second doped semiconductor layer.Type: GrantFiled: July 27, 2006Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Supratik Guha, Hendrik F. Hamann, Emanuel Tutuc
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Patent number: 7943928Abstract: An ESD protection structure includes a structure to be protected disposed in a semiconductor body. A region of a first conductivity type is disposed within the semiconductor body and a channel is disposed in the semiconductor body and extends through the region of the first conductivity type. A semiconductor of a second conductivity type is disposed within the channel adjacent the region of the first conductivity type such that the region of the first conductivity type and the semiconductor of the second conductivity type form a diode. At least one of the region of the first conductivity type and the semiconductor of the second conductivity type is electrically coupled to the structure to be protected.Type: GrantFiled: November 21, 2006Date of Patent: May 17, 2011Assignee: Infineon Technologies AGInventors: Michael Runde, Gernot Langguth, Klaus Roeschlau, Karlheinz Mueller
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Patent number: 7880763Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.Type: GrantFiled: August 29, 2008Date of Patent: February 1, 2011Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Naoki Yutani
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Patent number: 7833843Abstract: A method of forming a memory cell involves forming a semiconductor junction diode in series with an antifuse. The cell is programmed by rupture of the antifuse. The semiconductor junction diode comprises silicon, the silicon crystallized in contact with a silicide. The silicide apparently provides a template for crystallization, improving crystallinity and conductivity of the diode, and reducing the programming voltage required to program the cell. It is advantageous to reduce a dielectric layer (such as an oxide, nitride, or oxynitride) intervening between the silicon and the silicon-forming metal during the step of forming the silicide.Type: GrantFiled: December 19, 2006Date of Patent: November 16, 2010Assignee: SanDisk 3D LLCInventor: Scott Brad Herner
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Publication number: 20100140658Abstract: In a method of manufacturing a semiconductor device, a semiconductor substrate of a first conductivity type having first and second surfaces is prepared. Second conductivity type impurities for forming a collector layer are implanted to the second surface using a mask that has an opening at a portion where the collector layer will be formed. An oxide layer is formed by enhanced-oxidizing the collector layer. First conductivity type impurities for forming a first conductivity type layer are implanted to the second surface using the oxide layer as a mask. A support base is attached to the second surface and a thickness of the semiconductor substrate is reduced from the first surface. An element part including a base region, an emitter region, a plurality of trenches, a gate insulating layer, a gate electrode, and a first electrode is formed on the first surface of the semiconductor substrate.Type: ApplicationFiled: November 30, 2009Publication date: June 10, 2010Applicant: DENSO CORPORATIONInventors: Masaki Koyama, Yutaka Fukuda
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Patent number: 7714406Abstract: A method for manufacturing a semiconductor wafer electrostatic clamp, comprising providing a mounting plate, forming an insulative layer on an insulating portion of the mounting plate, forming a first electrode on a first portion of the mounting plate, forming a second electrode on a second portion of the mounting plate, forming a first segment having a first conductivity over the first electrode, forming a first region having a second conductivity over the first segment that creates an n-p type composite, forming a second segment having a third conductivity formed over the over the second electrode, forming a second region having a fourth conductivity formed over the second region that creates an p-n type composite.Type: GrantFiled: October 25, 2007Date of Patent: May 11, 2010Assignee: Axcelis Technologies, Inc.Inventors: Marvin Raymond LaFontaine, Michael Pharand, Leonard Michael Rubin, Klaus Becker
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Patent number: 7557405Abstract: An improved nonvolatile memory cell made by a method for fabricating a three dimensional monolithic memory with increased density. The memory cell includes at least a part of a first conductor, a semiconductor element, and at least a part of a second conductor. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements, preferably comprising two diode portions, optionally forming an antifuse above or below both of the diode portions, and then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.Type: GrantFiled: April 10, 2006Date of Patent: July 7, 2009Assignee: SanDisk 3D LLCInventors: S. Brad Herner, Maitreyee Mahajani
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Publication number: 20090085154Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: S. Brad Herner, Tanmay Kumar
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Patent number: 7414274Abstract: The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.Type: GrantFiled: September 26, 2007Date of Patent: August 19, 2008Assignee: SanDisk 3D LLPInventor: S. Brad Herner
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Patent number: 7402855Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.Type: GrantFiled: May 6, 2005Date of Patent: July 22, 2008Assignee: Sidense Corp.Inventor: Wlodek Kurjanowicz
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Patent number: 7381997Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.Type: GrantFiled: November 26, 2007Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
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Patent number: 7339186Abstract: Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric regions and are present only as a dummy. The connections between word and bit lines may also exist as transistors which turn on or turn off only when a gate voltage is applied. A number of these transistors are constructed in complementary fashion and/or have insulating regions built in and serve as a dummy.Type: GrantFiled: July 29, 2004Date of Patent: March 4, 2008Assignee: Infineon Technologies AGInventors: Hannes Mio, Franz Kreupl
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Patent number: 7335927Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.Type: GrantFiled: January 30, 2006Date of Patent: February 26, 2008Assignee: Internatioanl Business Machines CorporationInventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
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Publication number: 20060197188Abstract: Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes.Type: ApplicationFiled: January 18, 2006Publication date: September 7, 2006Inventors: Yoshimaro Fujii, Kouji Okamoto, Akira Sakamoto
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Patent number: RE47866Abstract: A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.Type: GrantFiled: February 4, 2016Date of Patent: February 18, 2020Assignee: Toshiba Memory CorporationInventors: Naoya Tokiwa, Hideo Mukai