Abstract: A method of forming a semiconductor device includes the following processes. First grooves are formed in a first insulating layer. A conductive material is formed which fills in each of the first grooves. A first mask is formed over the first insulating layer and the conductive material. The first mask has openings that define second grooves crossing the first grooves in plan view. The second grooves are formed in the first insulating layer and the conductive material by using the first mask. A plurality of conductive pillars are formed by removing a part of the conductive material in each of the first grooves.

Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

Abstract: A dynamic random access memory (DRAM) device has a metal-insulator-metal (MIM) capacitor electrically connected to a PN junction diode through a metal bridge for protecting the MIM capacitor from charge damage generated in back end of line (BEOL) plasma process.

Abstract: Field effect devices having a gate controlled via a nanotube switching element. Under one embodiment, a non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and each in electrical communication with a respective terminal. A channel region of a second semiconductor type of material is disposed between the source and drain region. A gate structure is disposed over an insulator over the channel region and has a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the gate structure and the terminal corresponding to the gate structure. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the gate structure and its corresponding terminal.

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Abstract: Disclosed herein is an improved memory device wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

Abstract: In one aspect, a semiconductor device includes an array of memory cells. Individual memory cells of the array include a capacitor having first and second electrodes, a dielectric layer disposed between the first and second electrodes. Select individual capacitors are energized so as to blow the dielectric layer to establish a connection between the first and second electrodes such that, after blowing the dielectric layer, the second electrode is coupled to a cell plate generator establishing a bias connection therebetween. Cell plate bias connection methods are also described.

Abstract: A seal ring (102) is formed in a manner to surround each ferroelectric capacitor (101). Additionally, a seal ring (103) is formed in a manner to surround a plurality of ferroelectric capacitors (101). Further, a seal ring (104) is formed in a manner to surround all of the ferroelectric capacitors (101) and along a dicing line (110) inside the dicing line (110).

Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.

Abstract: Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into the substrate to tie the upper active region to the substrate. The resulting memory cells are preferably used in dynamic random access memory (DRAM) devices.

Abstract: A semiconductor device having superior capacitance may include interconnections formed on a semiconductor substrate, an interlayer insulation layer on the interconnections and having vias exposing a portion of the top surface of the interconnections, a capacitor which may be on the interlayer insulation layer and having a bottom electrode, a dielectric layer pattern, and a top electrode which may be sequentially stacked, and a pad structure may be connected to the interconnections through the vias. The pad structure may include pads for bonding with external electronic devices and a first upper interconnection connected to the top electrode of the capacitor.

Abstract: A method of fabricating a semiconductor device includes forming a first interlayer insulating film including a storage node contact plug over a semiconductor substrate. A second interlayer insulating film is formed over the first interlayer insulating film and the storage node contact plug. A mask pattern is formed over the second interlayer insulating film to expose a storage node region. The second interlayer insulating film and the first interlayer insulating film is selectively etched to form a recess exposing a portion of the storage node contact plug. A lower storage node is formed in the recess. The storage node includes a concave structure that surrounds the exposed storage node contact plug. A dip-out process is performed to remove the second interlayer insulating film. A dielectric film is formed over the semiconductor substrate including the lower storage node. A plate electrode is deposited over the dielectric film to form a capacitor.

Abstract: An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.

Abstract: In a DRAM device having a capacitor and a method thereof, the capacitor included in the device is characterized to have a lower electrode that passes through a plurality of interlayer insulating layers. A first interlayer insulating layer is formed on a semiconductor substrate. A first contact plug layer is formed through the first interlayer insulating to electrically contact the semiconductor substrate. An insulating layer is formed on the first interlayer insulating layer. The insulating layer is etched to form the first interlayer insulating layer and a temporary storage node hole exposing the first contact plug. The first interlayer insulating layer exposed by the temporary storage node hole and portions of the first contact plug are simultaneously etched to form a storage node hole. A lower electrode layer is conformally formed on a surface of the semiconductor substrate having the storage node hole.

Abstract: The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes anodically etching individual capacitor electrode channels within a material over individual capacitor storage node locations on a substrate. The channels are at least partially filled with electrically conductive capacitor electrode material in electrical connection with the individual capacitor storage node locations. The capacitor electrode material is incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: A semiconductor memory device includes: first word lines; second word lines, each of the second word lines being electrically connected to a corresponding one of the first word lines; bit lines; and memory cells, each of the memory cells including a transistor and a capacitor. The semiconductor memory device includes: a first cell array portion in which the memory cells are arrayed; and a second cell array portion in which dummy cells, the first word lines and the bit lines are located in the same layout as the first cell array portion. In the second cell array portion, conductive plugs are provided, each of the conductive plugs connecting one of the first word lines and a corresponding one of the second word lines.

Abstract: A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas. The polysilicon gate areas couple word lines with capacitors associated with each arm portion of the cross-shaped active areas. Buried digit lines are coupled to body portions of the cross-shaped active areas. The word lines and digit lines provide a unique contact to each capacitor of the array of memory cells. Each memory cell has an area of 5F2. An electronic system and method for fabricating a memory cell are also disclosed.

Abstract: The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors. Individual of the capacitors include a storage node electrode, a capacitor dielectric region, and a cell electrode. The cell electrode is commonly shared among at least some of the plurality of memory cell capacitors within the memory array. The cell electrode within the memory array includes a conductor metal layer including at least one of elemental tungsten, a tungsten alloy, tungsten silicide and tungsten nitride. Polysilicon is received over the conductor metal layer. The conductor metal layer and the polysilicon are received over the storage node electrodes of said at least some of the plurality of memory cell capacitors. Other aspects and implementations are contemplated.

Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

Abstract: A semiconductor device includes: a transistor including source and drain diffusion-layers, a gate insulating film and a gate electrode; first and second plugs formed in a first interlayer-insulating film and connected to the source and drain diffusion-layers, respectively; a third plug extending through a second interlayer-insulating film and connected to the first plug; a first interconnection-wire formed on the second interlayer-insulating film and connected to the third plug; a second interconnection-wire formed on a third interlayer-insulating film and intersecting the first interconnection-wire; a fourth interlayer-insulating film; a hole extending through the fourth, third and second interlayer-insulating films, the hole being formed such that a side surface of the second interconnection-wire is exposed; and a fourth plug filling the hole via an intervening dielectric film and connected to the second plug, wherein a capacitor is formed using the fourth plug, the second interconnection-wire and the diele

Abstract: A capacitorless DRAM and methods of manufacturing and operating the same are provided. The capacitorless DRAM includes a source, a drain and a channel layer, formed on a substrate. A charge reserving layer is formed on the channel layer. The capacitorless DRAM includes a gate that contacts the channel layer and the charge reserving layer.

Abstract: Provided are a gate stack, a capacitorless dynamic random access memory (DRAM) including the gate stack and methods of manufacturing and operating the same. The gate stack for a capacitorless DRAM may include a tunnel insulating layer on a substrate, a first charge trapping layer on the tunnel insulating layer, an interlayer insulating layer on the first charge trapping layer, a second charge trapping layer on the interlayer insulating layer, a blocking insulating layer on the second charge trapping layer, and a gate electrode on the blocking insulating layer. The capacitorless DRAM may include the gate stack on the substrate, and a source and a drain in the substrate on both sides of the gate stack.

Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Abstract: A thin film transistor substrate and a fabricating method simplify a process and enlarge a capacitance value of a storage capacitor without any reduction of aperture ratio. A transparent first conductive layer and an opaque second conductive layer of a double-layer structured gate line are formed having a step coverage. A pixel electrode is provided on the gate insulating film within a pixel hole of said pixel area passing through the passivation film to be connected to the thin film transistor. A storage capacitor overlaps with the pixel electrode with having the gate insulating film therebetween and has a lower storage electrode protruded from the first conductive layer.

Abstract: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first-stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Abstract: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes a semiconductor pillar, a gate insulating layer formed on a portion of a surface of the semiconductor pillar, a gate electrode formed on the gate insulating layer, and source/drain regions formed on portions of the semiconductor pillar where the gate electrode is not formed, in which the gate electrode includes a first gate electrode, a second gate electrode, and an inter-gate insulating layer, in which the first gate electrode has a work function higher than that of the second gate electrode, in which the inter-gate insulating layer is formed between the first gate electrode and the second gate electrode, and in which the first gate electrode and the second gate electrode are electrically connected by a contact or a metal interconnection line. A portion of the second gate electrode having the work function lower than that of the first gate electrode is overlapped by the drain region.

Abstract: A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A method for making the interconnect structure maintains a preexisting geometry of the active region during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer.

Abstract: A capacitor is provided including a storage node contact pad and a storage electrode. The storage electrode includes at least two cylindrical conductive patterns. The at least two cylindrical conductive patterns are electrically coupled to a portion of a surface of the storage node contact pad. Related methods are also provided.

Abstract: A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

Abstract: This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions where are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region.

Abstract: There is provided a semiconductor device including a silicon substrate, a source/drain region formed in a surface layer of the silicon substrate, a first insulating film provided with a first hole on the first source/drain region, a conductive film formed on an inner surface of the first hole, a filler body, which is formed with a thickness to fill the first hole on the first conductive film, forms a first conduct plug together with the conductive film, and is formed of an insulating material with an upper surface being amorphous, and a capacitor, which is formed on the first contact plug and is provided with a lower electrode electrically connected to the conductive film, a capacitor dielectric film formed of a ferroelectric material, and an upper electrode.

Abstract: A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Abstract: Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of the component body. These components are grown directly in electrical communication lines. Moreover, these components are adapted for use in memory devices and are believed to not require the use of shallow trench isolation.

Abstract: Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into the substrate to tie the upper active region to the substrate. The resulting memory cells are preferably used in dynamic random access memory (DRAM) devices.

Abstract: Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate between the channel holes and the at least three layered impurity regions form a source region for the transistor.

Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.

Abstract: A method for forming a capacitor for use in a semiconductor device having electrode plugs surrounded by an insulating film and connected to underlying contact pads, includes sequentially forming an etch stop film and a mold oxide film on the insulating film and the electrode plugs, forming recesses in portions of the mold oxide film and the etching stopper film, the recesses exposing the electrode plugs, forming storage node electrodes in the recesses, filling the recesses in which the storage node electrodes are formed with an artificial oxide film, planarizing the storage node electrodes and the artificial oxide film so that the storage node electrodes are separated from one another, and selectively removing the mold oxide film and the artificial oxide film using a diluted hydrofluoric acid solution containing substantially no ammonium bifluoride.

Abstract: A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the dielectric formation, the lower capacitor electrode may be optionally annealed to improve capacitance.

Abstract: A semiconductor device includes: a semiconductor substrate; a first wiring formed above the semiconductor substrate with a first insulating film interposed therebetween; an MIM capacitor formed above the first insulating film; a second insulating film formed to cover the MIM capacitor; a second wiring formed on the second insulating film; and a guard ring buried in the second insulating film to surround the MIM capacitor.

Abstract: A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory including a lower electrode, a first insulating region formed in the same layer as the lower electrode, a ferroelectric film formed on the lower electrode and on the first insulating region, an upper electrode formed on the ferroelectric film, a second insulating region formed in the same layer as the upper electrode and a transistor. The first insulating region partitions the lower electrode. The second insulating region partitions the upper electrode. The transistor includes a first impurity region connected to the lower electrode and a second impurity region connected to the upper electrode. At least one of the first insulating region and the second insulating region is formed by insulating the lower electrode or the upper electrode.

Abstract: The method includes the steps of forming an upper electrode of a capacitor by patterning a second conductive film; forming a capacitor dielectric film by patterning a ferroelectric film; and forming a lower electrode by patterning a first conductive film. A step of forming the first conductive film includes the steps of forming a lower conductive layer made of a noble metal other than iridium over a first interlayer insulating film; and forming an upper conductive layer made of a conductive material, which is different from a material for the lower conductive layer, and which is other than platinum.

Abstract: A ferroelectric material includes a superlattice structure having lead zirconate layers and barium zirconate layers such that the superlattice structure has remanent polarization exhibiting a linearly positive dependency on a driving voltage.

Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

Abstract: An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a nitridization or anneal process. A dielectric layer of aluminum oxide (Al2O3), or a composite stack of interleaved layers of aluminum oxide and other metal oxide dielectric materials, is fabricated over the hemispherical grained polysilicon layer and after the optional nitridization or anneal process. The dielectric layer of aluminum oxide (Al2O3) or the aluminum oxide composite stack may be optionally subjected to a post-deposition treatment to further increase the capacitance and decrease the leakage current. A metal nitride upper electrode is formed over the dielectric layer or the composite stack by a deposition technique or by atomic layer deposition.

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract: A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

Abstract: The present invention provides a semiconductor device which can reduce consumption electric power even though high integration and technologies such as microfabrication further proceeds in future and a method of manufacturing the same. The present invention comprises a semiconductor substrate, a transistor formed on said semiconductor substrate, a first electric element electrically connected to said transistor, and a second electric element electrically connected to said first electric element, wherein said first electric element and said second electric element are connected in such way that at least two planes parallel with said semiconductor substrate surface and passing through both of said first electric element and said second electric element.