Capacitor Extending Under The Transistor (epo) Patents (Class 257/E27.09)
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Patent number: 8921911Abstract: A vertical semiconductor charge storage structure includes a substrate, at least one lower electrode, a dielectric layer and an upper electrode. The lower electrode includes a lower conductor, and a first side conductor and a second side conductor connected to the lower conductor. The first side conductor and the second side conductor are parallel to each other and form an included angle with the lower conductor. A height of the first side conductor from the substrate is greater than a height of the second side conductor from the substrate. The dielectric layer and the upper electrode are sequentially formed on surfaces of the substrate and the lower electrode. Accordingly, by forming the first side conductor and the second side conductor at different heights, an aperture ratio is increased to reduce difficulty in filling or deposition in subsequent processes to further enhance an overall yield rate.Type: GrantFiled: September 11, 2012Date of Patent: December 30, 2014Assignee: Rexchip Electronics CorporationInventors: Pin-Yuan Yu, Yi-Chun Shao, Chien-Hua Chu
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Patent number: 8659064Abstract: The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion.Type: GrantFiled: July 19, 2011Date of Patent: February 25, 2014Assignee: Micron Technology, Inc.Inventor: Yongjun Jeff Hu
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Publication number: 20130087840Abstract: A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Inventors: Kamal M. Karda, Suraj J. Mathew, Jaydip Guha
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Patent number: 8410534Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.Type: GrantFiled: February 8, 2012Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventor: Steven H. Voldman
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Patent number: 8258577Abstract: A CMOS inverter formed with narrowly spaced fins structures including transistors formed on sidewalls of each fin structure. A high-k dielectric material is deposited on the fins to provide mechanical stability to the fins and serve as a gate dielectric material. A mid gap metal gate layer may be formed on the high-k dielectric layer.Type: GrantFiled: June 4, 2009Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventor: Abhisek Dixit
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Patent number: 8129772Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.Type: GrantFiled: June 15, 2010Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventor: Steven H. Voldman
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Patent number: 7999330Abstract: The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion.Type: GrantFiled: June 24, 2005Date of Patent: August 16, 2011Assignee: Micron Technology, Inc.Inventor: Yongjun Jeff Hu
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Patent number: 7989857Abstract: An electronic device includes a transistor, wherein the electronic device can include a semiconductor layer having a primary surface, a channel region, a gate electrode, a source region, a conductive electrode, and an insulating layer lying between the primary surface of the semiconductor layer and the conductive electrode. The insulating layer has a first region and a second region, wherein the first region is thinner than the second region. The channel region, gate electrode, source region, or any combination thereof can lie closer to the first region than the second region. The thinner portion can allow for faster switch of the transistor, and the thicker portion can allow a relatively large voltage difference to be placed across the insulating layer. Alternative shapes for the transitions between the different regions of the insulating layer and exemplary methods to achieve such shapes are also described.Type: GrantFiled: December 17, 2008Date of Patent: August 2, 2011Assignee: Semiconductor Components Industries, LLCInventor: Gary H. Loechelt
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Patent number: 7791119Abstract: An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and heat treatment stability under a hydrogen-containing atmosphere is provided. An electro-resistance element includes an electro-resistance layer that has two or more states in which electric resistance values are different and being switchable from one of the two or more states into another by applying a predetermined voltage or current. The electro-resistance layer includes first and second elements being capable of forming a nitride, and nitrogen.Type: GrantFiled: March 30, 2007Date of Patent: September 7, 2010Assignee: Panasonic CorporationInventors: Akihiro Odagawa, Yoshihisa Nagano
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Publication number: 20080203403Abstract: The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure.Type: ApplicationFiled: December 19, 2007Publication date: August 28, 2008Inventors: Takayuki Kawahara, Masanao Yamaoka, Nobuyuki Sugii
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Patent number: 7371645Abstract: Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.Type: GrantFiled: December 30, 2005Date of Patent: May 13, 2008Assignee: Infineon Technologies AGInventors: Klaus Muemmler, Peter Baars, Stefan Tegen
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Patent number: 7235838Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.Type: GrantFiled: June 30, 2004Date of Patent: June 26, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Chieh Lin, Wen-Chin Lee
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Patent number: 7202518Abstract: An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is provided in the intermediate portion of the transistor for each cell. A polarization electrode is placed between the respective intermediate portions of the two transistors. This polarization electrode is capacitively coupled to the intermediate portion of each transistor and is used to store the first and second bits.Type: GrantFiled: June 25, 2004Date of Patent: April 10, 2007Assignee: STMicroelectronics S.A.Inventors: Francois Jacquet, Philippe Candellier, Robin Cerutti, Philippe Coronel, Pascale Mazoyer
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Patent number: 7126177Abstract: Disclosed are a semiconductor memory device, a semiconductor device, and a method for production thereof. The semiconductor memory device and semiconductor device do not need for a distance for alignment of lithography to make the contact hole with lithography to form the gate electrode. Hence the resulting devices have a reduced area for the cell array. The semiconductor memory device is composed of a substrate having trenches formed side by side, a plate electrode which is formed to a prescribed depth from the surface of the inner wall of the trench, a capacitor insulating film which covers the surface of the inner wall of the trench, a memory node electrode MN which fills the trench, with the capacitor insulating film interposed between them, and a memory node contact plug which is buried in a contact hole which is so made as to reach the memory node electrode from the surface of the semiconductor layer.Type: GrantFiled: December 29, 2004Date of Patent: October 24, 2006Assignee: Sony CorporationInventors: Yuzo Fukuzaki, Hiroshi Takahashi