Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: In a semiconductor device with a shared contact, a gate electrode is formed via a gate insulating film on a semiconductor substrate and a sidewall insulating film is formed on both side faces of the gate electrode. At least one of the surface parts of the semiconductor substrate adjacent to both sides of the gate electrode is removed beyond the lower part of the sidewall insulating film and to the underside of the gate electrode. Then, the gate insulating film exposed in the remove part is removed. An impurity-doped semiconductor layer is formed in the part where the semiconductor substrate and the gate insulating film have been removed.

Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The conductive features within the gate electrode level region are defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device.

Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes to be formed within a portion of a substrate, including a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by a central inactive region. The layout of the cell also includes a gate electrode level layout defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The gate electrode level layout corresponds to an entire gate electrode level of the cell.

Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The plurality of diffusion regions are separated from each other by one or more non-active regions of the substrate portion. The plurality of diffusion regions are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The number of conductive features within the gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction across the gate electrode level region.

Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Within a five wavelength photolithographic interaction radius within the gate electrode level region, a width size of the conductive features is less than 193 nanometers, which is the wavelength of light used in a photolithography process to fabricate the conductive features. The conductive features within the gate electrode level region form an equal number of PMOS and NMOS transistor devices.

Abstract: A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. Each of a number of interconnect level layouts is defined to pattern conductive features within corresponding interconnect levels above the gate electrode level.

Abstract: A restricted layout region includes a diffusion level layout including p-type and n-type diffusion region layout shapes separated by a central inactive region. The diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.

Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.

Abstract: A restricted layout region is defined to include a diffusion level layout that includes a plurality of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout of the restricted layout region. The plurality of diffusion region layout shapes include a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by a central inactive region. A gate electrode level layout is defined include a number of rectangular-shaped layout features placed to extend in only a first parallel direction, and defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.

Abstract: A semiconductor substrate according to one embodiment includes: a first transistor having a first gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the first gate insulating film and a first sidewall formed on a side face of the first gate electrode, the first gate insulating film comprising a high-dielectric constant material as a base material, a part of the first sidewall contacting with the first gate insulating film and containing Si and N; and a second transistor having a second gate insulating film formed on the semiconductor substrate, a second gate electrode formed on the second gate insulating film and a second sidewall formed on a side face of the second gate electrode so as to contact with the second gate insulating film, the second gate insulating film comprising a high-dielectric constant material as a base material, a part of the second sidewall contacting with the second gate insulating film and containing Si and N, wherein at least one of an abundance

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract: A semiconductor device includes a substrate portion and a number of diffusion regions defined within the substrate portion. The diffusion regions are separated from each other by a non-active region of the substrate portion. The semiconductor device includes a number of linear gate electrode segments defined to extend over the substrate portion in a single common direction. In one embodiment, the diffusion regions are defined in a non-symmetrical manner relative to a centerline of the substrate portion. In another embodiment, the substrate portion corresponds to a region of the semiconductor device in which first and second cells are defined, and respectively include diffusion shapes of different size. In another embodiment, one or more of the diffusion regions is defined to have a periphery formed by more than four orthogonally related sides.

Abstract: A first transfer transistor includes a first diffusion layer connected to a first bit line, and a second diffusion layer connected to a first storage node, the first diffusion layer is provided in a substrate, the second diffusion layer is provided in a bottom part of a recess provided in the substrate, a channel region of the first transfer transistor is offset with respect to the second diffusion layer toward the first storage node, and the offset part functions as a resistor.

Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.

Abstract: A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.

Abstract: A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides.

Abstract: A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, preferably 15 nm or less.

Abstract: An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask materi

Abstract: A method to fabricate an integrated circuit (IC) that includes a plurality of MOSFETs including at least one common gate FinFET device and at least one split gate FinFET device. A substrate having a semiconductor surface is provided. A plurality of fins are formed from the semiconductor surface including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height. Gate slacks are formed on the taller and shorter fins such that a gate electrode for the taller fin is a split gate electrode and a gate electrode for the shorter fin is a common gate electrode. Fabrication of the IC is completed, wherein the split gate FinFET includes the split gate electrode and the common gate FinFET device includes the common gate electrode.

Abstract: The invention relates to a semiconductor device (10) consisting of a substrate (11) and a semiconductor body (2) comprising a strip-shaped semiconductor region (3,3A,3B) of silicon in which a field effect transistor is formed, wherein a source region (4) of a first conductivity type, a channel region (33) of a second conductivity type opposed to the first, and a drain region (5) of the first conductivity type are arranged in succession, successively, seen in the longitudinal direction of the strip-shaped semiconductor region (3,3A,3B), and wherein the channel region (33) is provided with a gate dielectric (6), on which a first gate electrode (7) is present on a first vertical side of the strip-shaped semiconductor region (3,3A,3B), which gate electrode (7) is provided with a first connection region (7A), and on which a second gate electrode (8) is present on a second vertical side of the strip-shaped semiconductor region (3,3A,3B) positioned opposite the first vertical side, which second gate electrode (8) is

Abstract: Methods for fabricating a FinFET structure are provided. One method comprises forming a hard mask layer on a gate-forming material layer having a first portion and a second portion. A plurality of mandrels are fabricated on the hard mask layer and overlying the first portion and the second portion of the gate-forming material layer. A sidewall spacer material layer is deposited overlying the plurality of mandrels. The sidewall spacer material layer overlying the first portion of the gate-forming material layer is partially etched. Sidewall spacers are fabricated from the sidewall spacer material layer, the sidewall spacers being adjacent sidewalls of the plurality of mandrels. The plurality of mandrels are removed, the hard mask layer is etched using the sidewall spacers as an etch mask, and the gate-forming material layer is etched using the etched hard mask layer as an etch mask.

Abstract: A MOS transistor including a source region, a drain region, and a gate electrode has first and second partial isolation regions in one-end gate region and the other-end gate region, respectively, with a first tap region provided adjacent to the first partial isolation region, and a second tap region provided adjacent to the second partial isolation region. A full isolation region is provided in the whole area around the first and second partial isolation regions, first and second tap regions, and source and drain regions.

Abstract: A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.

Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.

Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Abstract: A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion.

Abstract: A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner sidewalls of the trench structure and depositing a polysilicon layer to fill the trench structure; introducing a nitrogen gas and performing a driving-in procedure to form a body structure; performing an implantation procedure to form a source layer; forming a dielectric layer on the trench structure and the source layer; etching the dielectric layer and the source layer to define a source structure and form a contact region; filling the contact region with a contact structure layer; and forming a conductive metal layer on the contact structure layer and the dielectric layer.

Abstract: SRAM devices and methods of fabricating the same are disclosed, by which a process margin and a degree of device integration are enhanced by reducing the number of contact holes of an SRAM device unit cell using local interconnections. A disclosed example device includes first and second load elements; first and second drive transistors; a common gate electrode connected in one body to a gate electrode of the first load element and a gate electrode of the first drive transistor to apply a sync signal to the gate electrodes; the common gate electrode overlapping with a junction layer of the second load element and a junction layer region of the second drive transistor; the common gate electrode being electrically connected to an upper line via a plug in one contact hole.

Abstract: In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.

Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.

Abstract: A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at least one SRAM cell with a gamma ratio of about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC, there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides a design structure of an IC embodied in a machine readable medium, the IC comprising at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.

Abstract: A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.

Abstract: A static random access memory at least includes: pluralities of transistors disposed on a substrate, each transistor at least includes a gate, a gate dielectric layer, a source doped region and a drain doped region, in which some of the source doped regions are used for connecting with a Vss voltage or a Vdd voltage, and a salicide layer disposed on the gates, the source doped regions except those source doped regions used for connecting a Vss voltage and a Vdd voltage and the drain doped regions.

Abstract: A semiconductor device has a pair of gate electrodes extending adjacent to and non-parallel to each other, a source and/or drain region located between the pair of gate electrodes for forming a pair of transistors with the gate electrodes, and a contact electrode disposed between the pair of gate electrodes in contact with the source and/or drain region in a contact area so that the center of the contact area is shifted from the center of the source and/or drain region in a direction along which the distance between the pair of gate electrodes becomes greater.

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

Abstract: A static random access memory means is provided. The SRAM memory means comprises a first pass-gate FET (T6) which is coupled between a first node (A) and a bitline-bar (BLB). A second pass-gate FET (T1) is coupled between a second node (B) and a bitline (BL). The second node (B) is coupled to the first pass-gate FET (T6) and the first pass-gate FET (T6) is switched according to the voltage (VB) at the second node (B). The first node (A) is coupled to the second pass-gate FET (T1). The second pass-gate FET (T1) is switched according to the voltage (VA) on the first node (A).

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: In an asymmetrical SRAM device, and a method of manufacturing the same, the asymmetrical SRAM device includes a semiconductor substrate on which a plurality of unit cell regions are defined, and a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate, wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions.