Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.

Abstract: A configurable computing system which uses near-memory and in-memory hardened logic blocks is described herein. The hardened logic blocks are incorporated into memory modules. The memory modules include an interface or communication logic to communicate between the configurable computing substrate and the memory module. In an implementation, the memory modules can include an on-die memory or other forms of non-configurable logic to enable more efficient processing for a variety of operations. In another implementation, the memory modules can include a portion of configurable computing substrate logic fabric to enable more efficient processing for a variety of operations. In another implementation, the memory modules can include an on-die memory and a portion of configurable computing substrate logic fabric to enable more efficient processing for a variety of operations.

Abstract: A method of adjusting port parameters. A source device establishes an initial output voltage swing and an emphasis level for output signals from a display port interface as a result of executing a link training process with a target device. A processor determines that a prescribed temperature threshold has been exceeded by a source device temperature. The output voltage swing and emphasis levels are set to different output voltage swing and emphasis levels as a consequence of determining that the prescribed temperature threshold has been exceeded.

Abstract: Clock networks constructed with variable drive strength clock drivers are prepared for tuning. The clock drivers are built from a smaller set of base standard cells. Locations of the input and output netlists of the macrocells are marked and reserved even through the extraction process. The macrocells are able to be flattened, generating a netlist with the base cells, and recombined during circuit simulation, thereby reducing the number of iterations, making the tuning flow more efficient. The clock network is initially tuned by adding or removing cross-links in the mesh to balance capacitive loads on each driver of the clock mesh.

Abstract: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a planar type device isolation gate electrode, and a width of the planar type device isolation gate electrode greater than a width of the device gate electrode.

Abstract: A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.

Abstract: Integrated circuit devices include a substrate having a semiconductor substrate region therein containing multiple well regions of different conductivity type. A first semiconductor well region of first conductivity type is provided in the semiconductor substrate region. This first semiconductor well region has a first plurality of transistor regions therein arranged in a first zig-zag pattern extending across the semiconductor substrate region. A second semiconductor well region of second conductivity type is also provided in the semiconductor substrate region. This second semiconductor well region has a second plurality of transistor regions therein arranged in a second zig-zag pattern extending across the semiconductor substrate region. This second zig-zag pattern is intertwined with the first zig-zag pattern.

Abstract: A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer.

Abstract: A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.

Abstract: A semiconductor memory device includes a memory cell transistor and a first MOS transistor. The memory cell transistor includes a first insulating film, a second insulating film, a control gate electrode, and a first diffusion layer. The first insulating film formed on the first active region. The second insulating film formed on the first insulating film. The control gate electrode formed so as to include a first metal film formed on the second insulating film and a first conductive film formed on the first metal film. The first MOS transistor includes a second conductive film, a second metal film, a third conductive film, and a second diffusion layer. The second conductive film formed on a second active region. The second metal film formed on the second conductive film. The third conductive film formed on a second metal film.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

Abstract: A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer.

Abstract: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.

Abstract: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor.

Abstract: A ferroelectric capacitor includes: a base substrate; a buffer layer formed above the base substrate; a lower electrode formed above the buffer layer; a ferroelectric layer formed above the lower electrode; and an upper electrode formed above the ferroelectric layer, wherein the buffer layer includes titanium (Ti) and cobalt (Co) as metal elements, and a metal element ratio x is 0.05?x<1, when Ti:Co=1?x:x.

Abstract: In a semiconductor device having line type active regions and a method of fabricating the semiconductor device, the semiconductor device includes a device isolation layer which defines the line type active regions in a in a semiconductor substrate. Gate electrodes which are parallel to each other and intersect the line type active regions are disposed over the semiconductor substrate. Here, the gate electrodes include both a device gate electrode and a recessed device isolation gate electrode. Alternatively, each of the gate electrodes is constituted of a device gate electrode and a plan type device isolation gate electrode, and a width of the plan type device isolation gate electrode greater than a width of the device gate electrode.

Abstract: Embodiments of the invention relate to semiconductor manufacturing process charge protection circuits, integrated circuits and to methods for manufacturing a semiconductor manufacturing process charge protection circuit. In an embodiment of the invention, a charge protection circuit includes a first terminal coupled to a charge receiving region, a second terminal providing a discharge path, and a rectifying circuit coupled between the first terminal and the second terminal, the rectifying circuit including at least two anti-parallel coupled rectifying components.

Abstract: A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

Abstract: An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed between the capacitor and the semiconductor component. Preferably, the semiconductor component is placed in proximity to the surface of the substrate and several superposed layers of insulating material cover the surface of the substrate and the semiconductor component. The capacitor is then placed within at least one layer of insulating material above the semiconductor component, and the screen is placed within an intermediate layer of insulating material between the layer incorporating the capacitor and the surface of the substrate.

Abstract: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetical to the shape of the drain diffusion layer region thereof below the selection gate transistor.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.