Infrared Imager (epo) Patents (Class 257/E27.143)
  • Publication number: 20130235210
    Abstract: A 3D wafer-integration uncooled infrared (IR) microbolometer focal plane array (FPA) sensor includes a first die with an FPA of uncooled IR microbolometers, a second die signal-processing layer. The dies are vertically aligned, stacked with 3D wafer bonding, and interconnected. Interconnection include vertical electrical interconnects. Separate optimized manufacturing processes are used for die, so that additional processing costs of the FPA die are leveraged and 3D integration is completed at wafer level, minimizing total device cost and maximizing die count per wafer.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 12, 2013
    Applicant: BAE SYSTEMS Information & Electronic Systems Integration Inc.
    Inventors: Rosanne H. Tinkler, Richard J. Blackwell, JR.
  • Publication number: 20130032912
    Abstract: A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 8143687
    Abstract: A broadband radiation detector includes a first layer having a first type of electrical conductivity type. A second layer has a second type of electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region. A third layer has the second type of electrical conductivity type and an energy bandgap responsive to radiation in a second spectral region comprising longer wavelengths than the wavelengths of the first spectral region. The broadband radiation detector further includes a plurality of internal regions. Each internal region may be disposed at least partially within the third layer and each internal region may include a refractive index that is different from a refractive index of the third layer. The plurality of internal regions may be arranged according to a regularly repeating pattern.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: March 27, 2012
    Assignee: Raytheon Company
    Inventors: Justin G. A. Wehner, Scott M. Johnson
  • Patent number: 7915652
    Abstract: An integrated infrared (IR) and full color complementary metal oxide semiconductor (CMOS) imager array is provided. The array is built upon a lightly doped p doped silicon (Si) substrate. Each pixel cell includes at least one visible light detection pixel and an IR pixel. Each visible light pixel includes a moderately p doped bowl with a bottom p doped layer and p doped sidewalls. An n doped layer is enclosed by the p doped bowl, and a moderately p doped surface region overlies the n doped layer. A transfer transistor has a gate electrode overlying the p doped sidewalls, a source formed from the n doped layer, and an n+ doped drain connected to a floating diffusion region. The IR pixel is the same, except that there is no bottom p doped layer. An optical wavelength filter overlies the visible light and IR pixels.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: March 29, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Douglas J. Tweet, Jon M. Speigle
  • Patent number: 7642620
    Abstract: It is an object of the present invention to provide a semiconductor apparatus for solving a trade-off between the area, power consumption, noise and accuracy of correction of a variation correction circuit that corrects variations in resistance and threshold voltage, etc. The present invention comprises a multi-value voltage generation circuit shared by a plurality of reading circuits, a multi-value voltage bus that supplies multi-value voltages to the reading circuits and switches that select a voltage suited to variation correction from multi-value voltages, wherein the multi-value voltages are distributed from the multi-value voltage generation circuit to the plurality of reading circuits, the switches select an optimum voltage for correction in the respective reading circuits to thereby correct variations in the elements.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: January 5, 2010
    Assignee: NEC Corporation
    Inventor: Akio Tanaka
  • Patent number: 7420147
    Abstract: A method of fabricating a multichannel plate is provided. The method includes providing a N layers, each layer having an array of wells formed therein. The N layers are aligned and stacked. The stack of N layers are sliced along a first and second line of the array of wells. The first line of the array of wells provides a first surface corresponding to a first array of channel openings of the MCP, and the second line of said array of wells provides a second surface corresponding to a second array of channel openings of the MCP. This method provides several functional benefits compared to conventional methods. These include, but are not limited to: the ability to produce well known and well characterized channels; the ability to produce well known and well characterized periods between channels; the ability to produce channels having any desired secondary electron emission enabling material therein; the ability to fabricate the substrate and/or final MCP of silicon.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 2, 2008
    Assignee: Reveo, Inc.
    Inventor: Sadeg M. Faris