Geometry Or Disposition Of Pixel-elements, Address Lines Or Gate-electrodes (epo) Patents (Class 257/E27.152)
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Patent number: 11966144Abstract: Tunable dielectric resonators for the modulation of freespace radiation and methods of using the resonators are provided. The dielectric resonators include a planar waveguide that supports a vertical Fabry-Perot resonance, a grating that supports a qBIC resonance, and a radiation absorbing material having an electronically or thermally tunable absorption at the qBIC resonant frequency. Using this resonator design, the intensity of the transmission and reflection of the qBIC resonance can be modulated by modulating the absorption properties of the absorbing material at the qBIC resonant frequency.Type: GrantFiled: July 5, 2022Date of Patent: April 23, 2024Assignee: Wiconsin ALumni Research FoundationInventors: Victor Brar, Seyoon Kim
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Patent number: 11948950Abstract: An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.Type: GrantFiled: April 7, 2021Date of Patent: April 2, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Mickael Fourel, Laurent-Luc Chapelon
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Patent number: 11860497Abstract: The present disclosure provides a pixel unit, wherein common signal lines connected to shared thin film transistors located in lens areas are constructed as first common signal lines, and common signal lines connected to shared thin film transistors located in lens splicing areas are constructed as second common signal lines. The pixel unit provided by the present disclosure can independently adjust partial voltages of the shared thin film transistors in the lens areas and the lens splicing areas, thereby relieving deterioration of Lens-Mura occurring in the lens splicing areas.Type: GrantFiled: June 3, 2020Date of Patent: January 2, 2024Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Ling Zhao
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Patent number: 11756978Abstract: In some examples, an apparatus comprises: a first photodiode to sense a first component of light associated with a first wavelength, and a second photodiode configured to sense a second component of the light associated with a second wavelength, the first component and the second component being associated with, respectively, a first wavelength and a second wavelength. The apparatus further comprises a first optical structure and a second optical structure positioned over, respectively, the first photodiode and the second photodiode. The first optical structure is configured to increase a propagation path of the first component of the light within the first photodiode and has a first optical property based on the first wavelength. The second optical structure is configured to increase a propagation path of the second component of the light within the second photodiode, and has a second optical property based on the second wavelength.Type: GrantFiled: February 24, 2021Date of Patent: September 12, 2023Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Qing Chao, Xinqiao Liu
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Patent number: 11695932Abstract: An apparatus includes at least one processor; and at least one memory including computer program code; wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to: provide an animation timing extension; wherein the animation timing extension links a graphics library transmission format animation to timed metadata and a metadata track of the timed metadata; wherein the metadata track of the timed metadata is listed with an object associated with moving picture media; and align at least one timeline of the moving picture media with at least one timeline of the graphics library transmission format animation; wherein a sample of the metadata track is used to manipulate an animation event.Type: GrantFiled: September 21, 2021Date of Patent: July 4, 2023Assignee: Nokia Technologies OyInventors: Lukasz Kondrad, Lauri Ilola
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Patent number: 11688751Abstract: A solid-state image pickup device includes: a filter section including filters that are disposed corresponding to respective pixels, and each allowing light of a color that corresponds to corresponding one of the pixels to transmit therethrough, in which the pixels are each configured to receive the light of the predetermined color; and a microlens array section including a plurality of microlenses each configured to collect the light for corresponding one of the pixels, in which the microlenses are stacked with respect to the filter section, and are arranged in an array pattern corresponding to the respective pixels. The microlenses have two or more shapes that are different from one another corresponding to the respective colors of the light to be received by the pixels, and each having an end that is in contact with the end of adjacent one of the microlenses.Type: GrantFiled: June 28, 2021Date of Patent: June 27, 2023Assignee: Sony Semiconductor Solutions CorporationInventor: Yoichi Ootsuka
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Patent number: 11626432Abstract: The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.Type: GrantFiled: July 3, 2019Date of Patent: April 11, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yusuke Otake, Toshifumi Wakano, Takuya Sano, Yusuke Tanaka, Keiji Tatani, Hideo Harifuchi, Eiichi Tauchi, Hiroki Iwashita, Akira Matsumoto
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Patent number: 11523099Abstract: Provided is a measurement device that includes a pixel including a light receiver, a plurality of storage sections, and an electric charge supplying section. The light receiver generates received-light electric charge by performing photoelectric conversion on the basis of light. The plurality of storage sections stores the received-light electric charge and the plurality of storage sections includes a first storage section and a second storage section. The electric charge supplying section selectively supplies the received-light electric charge generated by the light receiver to the plurality of storage sections. The measurement device includes a processor that generates a first detection value on the basis of an electric charge amount of the received-light electric charge stored in the first storage section, and generates a second detection value on the basis of an electric charge amount of the received-light electric charge stored in the second storage section.Type: GrantFiled: June 19, 2019Date of Patent: December 6, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Takuro Murase
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Patent number: 9508763Abstract: A radiation detector has a semiconductor substrate of a first conductivity type, a plurality of semiconductor regions of a second conductivity type making junctions with the semiconductor substrate, and a plurality of electrodes joined to the corresponding semiconductor regions. The electrodes cover the corresponding semiconductor regions, when viewed from a direction perpendicular to a first principal face. The semiconductor regions include a plurality of first and second semiconductor regions in a two-dimensionally array. The first semiconductor regions arrayed in a first direction in the two dimensional array out of the plurality of first semiconductor regions are electrically connected to each other, and the second semiconductor regions arrayed in a second direction intersecting with the first direction out of the plurality of second semiconductor regions are electrically connected to each other.Type: GrantFiled: August 6, 2012Date of Patent: November 29, 2016Assignee: HAMAMATSU PHOTONICS K.K.Inventor: Kazuhisa Yamamura
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Patent number: 8975638Abstract: The active matrix substrate is provided with: first and second scan lines (20a, 20b) that extend in a first direction; first and second signal lines (30a, 30b) that extend in a second direction; first and second pixels (10a, 10b) that are arranged adjacent to each other along the second direction; an auxiliary capacitor line (40); first and second pixel electrodes (60a, 60b); a first TFT (50a); a second TFT (50b); an auxiliary capacitor electrode (42) that is connected to the auxiliary capacitor line (40) and extends below the first and second pixel electrodes (60a, 60b); a first auxiliary capacitor counter electrode (62a) that is connected to the first pixel electrode (60a); and a second auxiliary capacitor counter electrode (62b) that is connected to the second pixel electrode (60b).Type: GrantFiled: December 22, 2011Date of Patent: March 10, 2015Assignee: Sharp Kabushiki KaishaInventors: Kazuyori Mitsumoto, Masahiro Yoshida, Satoshi Horiuchi
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Patent number: 8946717Abstract: A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.Type: GrantFiled: August 2, 2013Date of Patent: February 3, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Masahiko Hayakawa, Shunpei Yamazaki
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Patent number: 8940575Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.Type: GrantFiled: October 11, 2013Date of Patent: January 27, 2015Assignee: Sony CorporationInventor: Yasufumi Miyoshi
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Patent number: 8933495Abstract: The invention relates to time-delay and signal-integration linear image sensors (or TDI sensors). According to the invention, a pixel comprises a succession of several insulated gates covering a semiconducting layer, the gates of one pixel being separated from one another and separated from the gates of an adjacent pixel of another line by narrow uncovered gaps of a gate and comprising a doped region of a second type of conductivity covered by a doped superficial region of the first type; the superficial regions are kept at one and the same reference potential; the width of the narrow gaps between adjacent gates is such that the internal potential of the region of the second type is modified in the whole width of the narrow gap when a gate sustains the alternations of potential necessary for the transfer of charges from one pixel to the following one.Type: GrantFiled: January 26, 2012Date of Patent: January 13, 2015Assignee: E2V SemiconductorsInventor: Frederic Mayer
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Patent number: 8916915Abstract: Disclosed is a thin film transistor substrate which facilitates to improve output and transfer characteristics of thin film transistor, wherein the thin film transistor substrate comprises a thin film transistor comprising a lower gate electrode on a substrate, an active layer on the lower gate electrode, source and drain electrodes on the active layer, and an upper gate electrode on the source electrode, drain electrode and active layer, the upper gate electrode for covering a channel region defined by the source and drain electrodes; and a contact portion for electrically connecting the lower gate electrode with the upper gate electrode.Type: GrantFiled: November 26, 2012Date of Patent: December 23, 2014Assignee: LG Display Co., Ltd.Inventors: Jong Sik Shim, Woo Jin Nam, Hong Jae Shin, Min Kyu Chang
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Patent number: 8878264Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.Type: GrantFiled: June 30, 2011Date of Patent: November 4, 2014Assignee: Aptina Imaging CorporationInventors: Sergey Velichko, Jingyi Bai
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Patent number: 8866137Abstract: A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.Type: GrantFiled: February 3, 2012Date of Patent: October 21, 2014Assignee: Samsung Display Co., Ltd.Inventors: Jin-Won Lee, Woo Geun Lee, Kap Soo Yoon, Ki-Won Kim, Hyun-Jung Lee, Hee-Jun Byeon, Ji-Soo Oh
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Patent number: 8847285Abstract: In various embodiments, a charge-coupled device includes channel stops laterally spaced away from the channel by fully depleted regions.Type: GrantFiled: September 20, 2012Date of Patent: September 30, 2014Assignee: Semiconductor Components Industries, LLCInventor: Christopher Parks
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Patent number: 8841714Abstract: A solid state imaging device 1 is provided with a photoelectric conversion portion 2 having a plurality of photosensitive regions 7, and a potential gradient forming portion 3 having an electroconductive member 8 arranged opposite to the photosensitive regions 7. A planar shape of each photosensitive region 7 is a substantially rectangular shape. The photosensitive regions 7 are juxtaposed in a first direction intersecting with the long sides. The potential gradient forming portion 3 forms a potential gradient becoming higher along a second direction from one of the short sides to the other of the short sides of the photosensitive regions 7. The electroconductive member 8 includes a first region 8a extending in the second direction and having a first electric resistivity, and a second region 8b extending in the second direction and having a second electric resistivity smaller than the first electric resistivity.Type: GrantFiled: November 11, 2011Date of Patent: September 23, 2014Assignee: Hamamatsu Photonics K.K.Inventors: Tomohiro Ikeya, Yasuhito Yoneta, Hisanori Suzuki, Masaharu Muramatsu
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Patent number: 8835929Abstract: A pixel structure including a first thin film transistor (TFT), a second TFT and a storage capacitor is provided. The source electrode of the first TFT is connected to the gate electrode of the second TFT, and the semiconductor layer of the second TFT protrudes out two opposite side of the gate electrode of the second TFT. A thin film transistor including a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode is also provided. The capacitance compensation structure is electrically connected to the gate electrode. The semiconductor layer partially overlaps the gate electrode, and extends to overlap the capacitance compensation structure.Type: GrantFiled: April 7, 2013Date of Patent: September 16, 2014Assignee: AU Optronics Corp.Inventors: Peng-Bo Xi, Yu-Chi Chen
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Patent number: 8658457Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.Type: GrantFiled: June 16, 2011Date of Patent: February 25, 2014Assignee: Sony CorporationInventor: Yasufumi Miyoshi
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Patent number: 8624301Abstract: In a back-illuminated solid-state image pickup device including a semiconductor substrate 4 having a light incident surface at a back surface side and a plurality of charge transfer electrodes 2 disposed at a light detection surface at an opposite side of the semiconductor substrate 4 with respect to the light incident surface, a plurality of openings OP for transmitting light are formed between charge transfer electrodes 2 that are adjacent to each other. Also, a plurality of openings OP for transmitting light may be formed inside each charge transfer electrode 2.Type: GrantFiled: March 23, 2010Date of Patent: January 7, 2014Assignee: Hamamatsu Photonics K.K.Inventors: Hisanori Suzuki, Yasuhito Yoneta, Masaharu Muramatsu, Koei Yamamoto
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Patent number: 8519456Abstract: A solid-state image pickup device in which electric charges accumulated in a photodiode conversion element are transferred to a second diffusion layer through a first diffusion layer.Type: GrantFiled: September 28, 2010Date of Patent: August 27, 2013Assignee: Sony CorporationInventors: Atsushi Masagaki, Ikuhiro Yamamura
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Patent number: 8344389Abstract: An optoelectonice device array includes a plurality of packages, each enclosing an optoelectronic device, and positioned in at least one row. Each package overlaps at least one adjacent package, and may be hermetically sealed.Type: GrantFiled: January 29, 2010Date of Patent: January 1, 2013Assignee: General Electric CompanyInventors: Donald Seton Farquhar, Michael Scott Herzog
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Publication number: 20120193683Abstract: The invention relates to time-delay and signal-integration linear image sensors (or TDI sensors). According to the invention, a pixel comprises a succession of several insulated gates covering a semiconducting layer, the gates of one pixel being separated from one another and separated from the gates of an adjacent pixel of another line by narrow uncovered gaps of a gate and comprising a doped region of a second type of conductivity covered by a doped superficial region of the first type; the superficial regions are kept at one and the same reference potential; the width of the narrow gaps between adjacent gates is such that the internal potential of the region of the second type is modified in the whole width of the narrow gap when a gate sustains the alternations of potential necessary for the transfer of charges from one pixel to the following one.Type: ApplicationFiled: January 26, 2012Publication date: August 2, 2012Applicant: E2V SEMICONDUCTORSInventor: Frederic MAYER
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Patent number: 8218043Abstract: The prevent invention is to provide a solid-state imaging device having a electrode configuration applicable to a progressive scan, and able to reduce a obstruction of incident light at the periphery of a light receiving portion, a method of producing the same, a camera including the same. A first transfer electrode, a second transfer electrode, and a third transfer electrode which have a single layer transfer electrode configuration are repeatedly arranged in a vertical direction. The first transfer electrodes are connected in a horizontal direction by an inter-pixel interconnection formed in the same layer. Shunt interconnections are formed in the horizontal direction and in the vertical direction above the transfer layers. The shunt interconnection connected to the second transfer interconnection is formed on the inter-pixel interconnection. The shunt interconnection connected to the third transfer electrode is formed above the transfer electrodes.Type: GrantFiled: July 6, 2009Date of Patent: July 10, 2012Assignee: Sony CorporationInventor: Hideo Kanbe
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Patent number: 8207007Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.Type: GrantFiled: August 18, 2008Date of Patent: June 26, 2012Assignee: Sony CorporationInventor: Yasufumi Miyoshi
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Patent number: 8163591Abstract: A backside illuminated image sensor includes a photodiode, formed below the top surface of a semiconductor substrate, for receiving light illuminated from the backside of the semiconductor substrate to generate photoelectric charges, a reflecting gate, formed on the photodiode over the front upper surface of the semiconductor substrate, for reflecting light illuminated from the backside of the substrate and receiving a bias to control a depletion region of the photodiode, and a transfer gate for transferring photoelectric charges from the photodiode to a sensing node of a pixel.Type: GrantFiled: November 30, 2010Date of Patent: April 24, 2012Assignee: Intellectual Ventures II LLCInventors: Sung-Hyung Park, Ju-Il Lee
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Patent number: 8102017Abstract: An image sensor may comprise circuitry, a first lower electrode, a photodiode, an upper electrode, a second lower electrode, and an upper interconnection. The circuitry may comprise a first lower interconnection and a second lower interconnection over a dielectric of a substrate. The first lower electrode, the photodiode, and the upper electrode may be sequentially formed over the first lower interconnection. The second lower electrode may comprise a passivation layer over the second lower interconnection. The upper interconnection may be formed over the second lower electrode and electrically connected to the upper electrode.Type: GrantFiled: December 22, 2008Date of Patent: January 24, 2012Assignee: Dongbu HiTek Co., Ltd.Inventor: Ki Jun Yun
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Patent number: 8044478Abstract: Provided is an image sensor. The image sensor can include a readout circuitry on a first substrate. An interlayer dielectric is formed on the first substrate, and comprises a lower line therein. A crystalline semiconductor layer is bonded to the interlayer dielectric. A photodiode can be formed in the crystalline semiconductor layer, and comprises a first impurity region and a second impurity region. A via hole can be formed passing through the crystalline semiconductor layer and the interlayer dielectric to expose the lower line. A plug is formed inside the first via hole to connect with only the lower line and the first impurity region. A device isolation region can be formed in the crystalline semiconductor layer to separate the photodiode according to unit pixel.Type: GrantFiled: September 5, 2008Date of Patent: October 25, 2011Assignee: Dongbu Hitek Co., Ltd.Inventor: Joon Hwang
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Patent number: 7955908Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.Type: GrantFiled: February 13, 2007Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hye-Young Ryu, Young-Hoon Yoo, Jang-Soo Kim, Sung-Man Kim, Kyung-Wook Kim, Hyang-Shik Kong, Young-Goo Song
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Patent number: 7910964Abstract: A part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first transfer gate electrode functions as a first transfer channel, and the surface buried region directly under a second transfer gate electrode functions as a second transfer channel. Signal charges are alternately transferred to an n-type first floating drain region and a second floating drain region through the first and second floating transfer channels.Type: GrantFiled: August 30, 2006Date of Patent: March 22, 2011Assignees: National University Corporation Shizuoka University, Sharp Kabushiki KaishaInventors: Shoji Kawahito, Mitsuru Homma
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Patent number: 7902550Abstract: A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the surface of a pixel electrode is performed by the same photomask as that used for forming a channel etch type TFT, in which the convex portion is formed in order to provide unevenness to the surface of the pixel electrode and give light scattering characteristics.Type: GrantFiled: January 25, 2008Date of Patent: March 8, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 7880206Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.Type: GrantFiled: July 17, 2009Date of Patent: February 1, 2011Assignee: Crosstek Capital, LLCInventor: Hee-Jeong Hong
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Patent number: 7847326Abstract: A backside illuminated image sensor includes a photodiode, formed below the top surface of a semiconductor substrate, for receiving light illuminated from the backside of the semiconductor substrate to generate photoelectric charges, a reflecting gate, formed on the photodiode over the front upper surface of the semiconductor substrate, for reflecting light illuminated from the backside of the substrate and receiving a bias to control a depletion region of the photodiode, and a transfer gate for transferring photoelectric charges from the photodiode to a sensing node of a pixel.Type: GrantFiled: June 27, 2008Date of Patent: December 7, 2010Inventors: Sung-Hyung Park, Ju-Il Lee
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Patent number: 7777228Abstract: An array substrate for a liquid crystal display device comprises a gate line on a substrate having a pixel region; a gate insulating layer on the gate line; a data line crossing the gate line to define the pixel region and formed on the gate insulating layer; a thin film transistor in the pixel region and connected to the gate line and the data line; a passivation layer on the thin film transistor and the data line and having a groove extending along boundary portion of the pixel region and exposing the gate insulating layer; and a pixel electrode in the pixel region and connected to the thin film transistor.Type: GrantFiled: June 27, 2007Date of Patent: August 17, 2010Assignee: LG Display Co., Ltd.Inventor: Ji-Hyun Jung
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Patent number: 7763899Abstract: An electro-optical device provided with a plurality of pixel sections, includes: a first substrate having a plurality of light-emitting elements to configure the plurality of pixel sections; a second substrate having a driving circuit to control light emission of the plurality of light-emitting elements, respectively, and disposed so as to face an element forming surface of the first substrate; and a plurality of conductive connectors provided between the first substrate and the second substrate, and electrically connect the plurality of light-emitting elements, respectively, to the driving circuit. The plurality of conductive connectors are disposed in a staggered manner at least along a first arrangement direction of the plurality of pixel sections.Type: GrantFiled: August 2, 2006Date of Patent: July 27, 2010Assignee: Seiko Epson CorporationInventor: Daisuke Abe
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Patent number: 7750883Abstract: A liquid crystal display device including a liquid crystal panel, a gate driver configured to supply gate signals to gate lines on the liquid crystal panel, a data driver configured to supply data voltages to data lines on the liquid crystal panel, and a partial controller configured to control the gate driver to intercept a part of the gate signals to be supplied to the gate lines.Type: GrantFiled: December 28, 2006Date of Patent: July 6, 2010Assignee: LG Display Co., Ltd.Inventors: Su Hwan Moon, Do Heon Kim, Ji Eun Chae
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Patent number: 7692222Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.Type: GrantFiled: November 7, 2006Date of Patent: April 6, 2010Assignee: Raytheon CompanyInventors: Kamal Tabatabaie, Robert B. Hallock
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Patent number: 7663144Abstract: A solid-state imaging device is provided and has a plurality of pixel parts including three photoelectric conversion layers stacked above a semiconductor substrate, the plurality of pixel parts being arranged above the semiconductor substrate. The three photoelectric conversion layers, respectively, included in one pixel part are interposed between pixel electrode layers and opposing electrode layers. A region thus interposed is made a pixel region that generates a signal charge for formation of one pixel data. The pixel region includes a convex portion and a concave portion as viewed in plane view, and a part of the convex portion is arranged in a manner to put in a concave portion in a pixel region of an adjacent pixel part.Type: GrantFiled: February 6, 2006Date of Patent: February 16, 2010Assignee: Fujifilm CorporationInventor: Takeshi Misawa
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Patent number: 7629611Abstract: A current storing circuit capable of having a small area, a simple structure with the small number of devices, a low consumption current operation and high yield in manufacturing is provided. Applying the current storing circuit to the current-driving type of display device such as an OLED display device can improve the aperture rate of pixels and reliability of the display device as well as highly functionalize the display device. The invention is characterized by using a new semiconductor element in a shape of a transistor having plural drains or sources. When the semiconductor elements is used for both of a writing element and a driving element, reading in and storing a current value and outputting the current can be performed by only the two semiconductor elements, so that the area occupied by the devices would be easily reduced significantly.Type: GrantFiled: November 7, 2002Date of Patent: December 8, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kazutaka Inukai
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Patent number: 7605411Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.Type: GrantFiled: July 17, 2008Date of Patent: October 20, 2009Assignee: Fujifilm CorporationInventors: Hirokazu Shiraki, Makoto Kobayashi, Katsumi Ikeda
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Patent number: 7582900Abstract: An additional circuit is formed on a glass substrate, and a passivation film is deposited thereon. After an insulation film is deposited on the passivation film, a contact hole is formed, and a signal line is deposited and connected to the additional circuit. After the signal line and the insulation film are patterned, an organic insulation film is formed, to thereby have a surface of an uneven configuration depending on a step formed by the signal line and the insulation film. A reflective electrode is formed on the organic insulation film, to thereby have a surface of an uneven configuration. This eliminates the need to perform a photolithography process step for the formation of the surface of the organic insulation film in the uneven configuration, thereby reducing manufacturing costs.Type: GrantFiled: January 18, 2007Date of Patent: September 1, 2009Assignee: Mitsubishi Electric CorporationInventors: Yasuyoshi Itoh, Kaoru Motonami
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Patent number: 7575992Abstract: A method of forming a micro pattern in a semiconductor device is disclosed. An oxide film mask is divided into a cell oxide film mask and a peri oxide film mask. Therefore, a connection between the cell and the peri region can be facilitated. A portion of a top surface of a first oxide film pattern between a region in which a word line will be formed and a region in which a select source line will be formed is removed. Accordingly, the space can be increased and program disturbance in the region in which the word line will be formed can be prevented. Furthermore, a pattern having a line of 50 nm and a space of 100 nm or a pattern having a line of 100 nm and a space of 50 nm, which exceeds the limitation of the ArF exposure equipment, can be formed using a pattern, which has a line of 100 nm and a space of 200 nm and therefore has a good process margin and a good critical dimension regularity.Type: GrantFiled: September 8, 2006Date of Patent: August 18, 2009Assignee: Hynix Semiconductor Inc.Inventors: Woo Yung Jung, Jong Hoon Kim
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Patent number: 7576375Abstract: A thin film transistor array includes a substrate, scan lines, data lines, thin film transistors, upper electrodes and pixel electrodes. The scan lines and the data lines are disposed on the substrate to define pixel areas on the substrate. The thin film transistors are disposed inside corresponding pixel areas and are driven through corresponding scan line and data lines. The upper electrodes are disposed within various pixel areas above the scan lines. The upper electrode has a protrusion protruding beyond the edge of a corresponding scan line. The pixel electrode is disposed within a corresponding pixel area and electrically connected to a corresponding thin film transistor and upper electrode, wherein each pixel electrode has at least a slit formed therein, the slit has an end portion near the corresponding scan line, and the end portion is completely shielded by the protrusion of the corresponding upper electrode.Type: GrantFiled: October 23, 2008Date of Patent: August 18, 2009Assignee: Au Optronics CorporationInventor: Han-Chung Lai
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Patent number: 7491561Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal.Type: GrantFiled: November 27, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: James W. Adkisson, Mark D. Jaffe, Robert K. Leidy
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Publication number: 20090001427Abstract: A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe
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Publication number: 20080237652Abstract: A method of manufacturing a solid image pick-up device comprising a photoelectronic conversion portion, a charge transfer portion and a peripheral circuit portion, the method comprising: forming a pattern comprising a first layer silicon conductive film to a surface of a semiconductor, the first layer silicon conductive film forming: a first electrode; and a first layer interconnection for the photoconductive conversion portion and the peripheral circuit portion; forming an insulative film at least to a side wall of the first electrode; forming a second silicon conductive film being to form a second electrode to the semiconductor substrate; coating a resist over the semiconductor substrate by a spin coating method; and planarizing the second layer silicon conductive film by a resist etching-back method, wherein the pattern further comprises at least one dummy pattern, and a surface level of the resist is not below a predetermined value over the semiconductor substrate.Type: ApplicationFiled: May 19, 2005Publication date: October 2, 2008Inventors: Teiji Azumi, Takanori Sato
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Patent number: 7382003Abstract: A solid-state image pick-up unit comprises: a semiconductor substrate comprising an area in which a photoelectric converting portion is formed; and an electric charge transfer portion that transfers an electric charge formed by the photoelectric converting portion, wherein the electric charge transfer portion comprises: an electric charge transfer electrode including a first layer electrode and a second layer electrode; and a gate oxide film, the gate oxide film comprises a second gate oxide film formed under the second layer electrode, the second gate oxide film comprising an ONO film which comprises a SiO film, a SiN film and a SiO film in this order, and the second gate oxide film is continuously formed to cover whole of a region between the first layer electrode and the second layer electrode and a region under the second layer electrode.Type: GrantFiled: March 14, 2006Date of Patent: June 3, 2008Assignee: Fujifilm CorporationInventor: Ryoichi Homma
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Patent number: 7224008Abstract: The invention relates to a manufacturing method for an insulated gate semiconductor device cell, comprising the steps of forming a cell window (3) in a layered structure that is located on top of a semiconductor substrate (1), forming at least one process mask that partially covers the cell window (3). In forming the cell window (3), at least one strip (41, 42) of the layered structure is left to remain inside the cell window (3) and at least one strip (41, 42) is used to serve as an edge for the at least one process mask (51, 52). The invention further relates to an insulated gate semiconductor device, comprising a semiconductor substrate (1) having an essentially planar top surface and an insulated gate formed on the top surface by a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41, 42) of the layered structure (2) is disposed on a third area of the top surface between an edge of the insulated gate and a first main contact (6).Type: GrantFiled: December 9, 2003Date of Patent: May 29, 2007Assignee: ABB Schweiz AGInventors: Munaf Rahimo, Christoph Von Arx
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Patent number: 7193252Abstract: In a photosensitive part 10, arranged from pixels A aligned in n rows and m columns, supply wiring lines 13a and 13b, which are electrically connected and apply transfer voltages to transfer electrodes 12a to 12d, formed of polycrystalline silicon, are installed so as to cover parts of the top surfaces of light-shielded pixels D. Dead zones for installing supply wiring lines, which existed priorly at the respective end parts in a horizontal direction of a photosensitive part, can thereby be eliminated and the photosensitive part can be made wide. Also, in the case where a plurality of the solid-state image pickup devices are used upon being made adjacent each other in the horizontal direction, parts at which image pickup is not carried out can be lessened. Also, the amount of lowering of the amounts of incident light on light-shielded pixels D can be corrected based on the output signals from light-shielded pixels D or other pixels A.Type: GrantFiled: May 2, 2003Date of Patent: March 20, 2007Assignee: Hamamatsu Photonics K.K.Inventor: Kazuhisa Miyaguchi