Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Abstract: A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect connected to the interconnect; a forward diode and a backward diode connected in parallel to the interconnect; an NMIS whose drain is connected to the output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate is grounded through an upper metal interconnect; a PMIS whose drain is connected to the input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate of the NMIS; and a second antenna connected to the gate of the PMIS.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

Abstract: Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.

Abstract: A description is given of a concept for reducing shunt currents in a semiconductor body.

Abstract: An N-type diffusion layer fixed at a potential equal to or above 0V is provided in a segregating region between terminals, and a P-type diffusion layer having a potential equal to that of the N-type diffusion layer on an N-type well constitute a drain of a transistor.

Abstract: An n-type isolation structure is disclosed which includes an n-type BISO layer in combination with a shallow n-well, in an IC. The n-type BISO layer is formed by implanting n-type dopants into a p-type IC substrate in addition to a conventional n-type buried layer (NBL), prior to growth of a p-type epitaxial layer. The n-type dopants in the BISO implanted layer diffuse upward from the p-type substrate to between one-third and two-thirds of the thickness of the p-type epitaxial layer. The shallow n-type well extends from a top surface of the p-type epitaxial layer to the n-type BISO layer, forming a continuous n-type isolation structure from the top surface of the p-type epitaxial layer to the p-type substrate. The width of the n-type BISO layer may be less than the thickness of the epitaxial layer, and may be used alone or with the NBL to isolate components in the IC.

Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

Abstract: Channel stop sections are formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.

Abstract: A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a semiconductor die from other elements on the semiconductor die.

Abstract: A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial layer with a low concentration impurity provided on the semiconductor substrate, where a trench coupled to the semiconductor substrate is provided in the epitaxial layer with the low concentration impurity. And the semiconductor device further includes a high concentration impurity region of the first type conductivity having the same type conductivity as the type of the semiconductor substrate formed in at least the epitaxial layer with the low concentration impurity along an inner wall of the trench and coupled to the semiconductor substrate with the high concentration impurity of a first type conductivity, and contacts formed on the high concentration impurity region of the first type conductivity.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: A semiconductor sensing device for sensing presence, absence or level of species-of-interest in the environment is disclosed. The semiconductor sensing device comprises at least one layer of molecules deposited thereon. The molecules are electrically-responsive to the species-of-interest in a manner such that when the molecules interact with the species-of-interest, a reverse breakdown voltage characterizing the semiconductor sensing device is modified.

Abstract: A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.

Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.

Abstract: A semiconductor sensing device for sensing presence, absence or level of species-of-interest in the environment is disclosed. The semiconductor sensing device comprises at least one layer of molecules deposited thereon. The molecules are electrically-responsive to the species-of-interest in a manner such that when the molecules interact with the species-of-interest, a reverse breakdown voltage characterizing the semiconductor sensing device is modified.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.

Abstract: A power semiconductor device includes a plurality of trenches formed within a semiconductor body, each trench including one or more electrodes formed therein. In particular, according to embodiments of the invention, the plurality of trenches of a semiconductor device may include one or more gate electrodes, may include one or more gate electrodes or one or more source electrodes, or may include a combination of both gate and source electrodes formed therein. The trenches and electrodes may have varying depths within the semiconductor body.

Abstract: A semiconductor device is provided, which includes a substrate; a P-N column layer disposed on the substrate; a second conductivity type epitaxial layer disposed on the P-N column layer. The P-N column layer includes first conductivity type columns and second conductivity type columns, which are alternately arranged. Each column has a tapered shape. A portion of the first conductivity type column located around the substrate has a smaller impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer. A portion of the second conductivity type column located around the substrate has a larger impurity concentration than another portion of the first conductivity type column located around the second conductivity type epitaxial layer.

Abstract: A crossbar structure includes a first layer or layers including first p-type regions and first n-type regions, a second layer or layers including second p-type regions and second n-type regions, and a resistance programmable material formed between the first layer(s) and the second layer(s), wherein the first layer(s) and the second layer(s) include first and second intersecting wiring portions forming a crossbar array.

Abstract: A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region.

Abstract: The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.

Abstract: An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.

Abstract: A first insulation film is made of a silicon material and is provided on a semiconductor base. A second insulation film is made of an organic material and is provided on the first insulation film. The second insulation film is thicker than the first insulation film. A third insulation film is thinner than the second insulation film and is provided on the second insulation film. The third insulation film is made of a silicon material and has a moisture resistance property. A fourth insulation film is made of an organic material. The fourth insulation film is provided on the third insulation film to prevent a damage on the third insulation film. A wiring layer is provided on the fourth insulation film.

Abstract: A driving circuit and a data-line driver is provided which are capable of improving the tolerance to noise between adjacent terminals by using a conventional CMOS process while keeping the chip size small, because a high-density N-diffusion layer (116) is provided in an isolation region (115) to minimize a collector current of a parasitic NPN transistor (102).

Abstract: An N− type epitaxial layer is formed on a P− type silicon substrate. Trenches are created so as to penetrate N− type epitaxial layer and so as to reach to a predetermined depth of P− type silicon substrate. Thermal oxide films are formed on the sidewalls of trenches. Buried polysilicon films are formed so as to fill in trenches. Thermal oxide films are formed having an approximately constant film thickness ranging from the bottoms to the edges of the openings of trenches so as not to give stress to N− type epitaxial layers. Thereby, a semiconductor device wherein a leak current is prevented can be gained.