Anode Or Cathode Regions Of Thyristors Or Gated Bipolar-mode Devices (epo) Patents (Class 257/E29.036)
  • Patent number: 8878236
    Abstract: In a first embodiment, an ultra-fast breakover diode has a turn on time TON that is less than 0.3 microseconds, where the forward breakover voltage is greater than +400 volts and varies less than one percent per ten degrees Celsius change. In a second embodiment, a breakover diode has a reverse breakdown voltage that is greater, in absolute magnitude, than the forward breakover voltage, where the forward breakover voltage is greater than +400 volts. In a third embodiment, a string of series-connected breakover diode dice is provided, along with a resistor string, in a packaged circuit. The packaged circuit acts like a single breakover diode having a large forward breakover voltage and a comparably large reverse breakdown voltage, even though the packaged circuit includes no discrete high voltage reverse breakdown diode. The packaged circuit is usable to supply a triggering current to a thyristor in a voltage protection circuit.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: November 4, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Patent number: 8866125
    Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: October 21, 2014
    Assignee: STC.UNM
    Inventor: Stephen D. Hersee
  • Patent number: 8664690
    Abstract: A bi-directional triode thyristor (TRIAC) device for high voltage electrostatic discharge (ESD) protection may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. The portion of the N-type well region that is interposed between the two P-type well regions may comprise one or more P-type portions, such as a P+ doped plate or a P-type implant.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: March 4, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu, Wing-Chor Chan, Shyi-Yuan Wu
  • Patent number: 8420454
    Abstract: An embodiment of a power device having a first current-conduction terminal, a second current-conduction terminal, a control terminal receiving, in use, a control voltage of the power device, and a thyristor device and a first insulated-gate switch device coupled in series between the first and the second conduction terminals; the first insulated-gate switch device has a gate terminal coupled to the control terminal, and the thyristor device has a base terminal. The power device is further provided with: a second insulated-gate switch device, coupled between the first current-conduction terminal and the base terminal of the thyristor device, and having a respective gate terminal coupled to the control terminal; and a Zener diode, coupled between the base terminal of the thyristor device and the second current-conduction terminal so as to enable extraction of current from the base terminal in a given operating condition.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: April 16, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cesare Ronsisvalle, Vincenzo Enea
  • Patent number: 8390124
    Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: March 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Inoue, Yoshihiro Hayashi, Kishou Kaneko
  • Patent number: 8093622
    Abstract: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hideaki Kawahara, Toshimi Satoh, Toshiyuki Tani
  • Patent number: 8080830
    Abstract: A semiconductor device includes: a bulk semiconductor substrate; a thyristor formed in the bulk semiconductor substrate; a gate electrode formed at the third region; and a well region. The thyristor included a first region of a first conduction type, a second region of a second conduction type opposite to the first conduction type, a third region of the first conduction type, and a fourth region of the second conduction type, junctioned in order. The well region of the second conduction type is formed in the bulk semiconductor substrate, the third region is formed in the well region. A first voltage is impressed on the first region side of the thyristor, a second voltage higher than the first voltage is impressed on the fourth region side of the thyristor, and a voltage higher than or equal to the first voltage is impressed on the well region.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: December 20, 2011
    Assignee: Sony Corporation
    Inventor: Taro Sugizaki
  • Patent number: 7910949
    Abstract: A power semiconductor device includes a conductive board and a switching element mounted on the conductive board and electrically connected thereto. The power semiconductor device also includes an integrated circuit mounted on the conductive board at a distance from the switching element and electrically connected thereto. The switching element turns ON/OFF a connection between first and second main electrodes in response to a control signal inputted to a control electrode. The integrated circuit includes a control circuit which controls ON/OFF the switching element and a back side voltage detection element which detects a voltage of the back side of the integrated circuit.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: March 22, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yukio Yasuda, Atsunobu Kawamoto, Shinsuke Goudo
  • Patent number: 7824967
    Abstract: A monolithically integrated light-activated thyristor in an n-p-n-p-n-p sequence consists of a four-layered thyristor structure and an embedded back-biased PN junction structure as a turn-off switching diode. The turn-off switching diode is formed through structured doping processes and/or depositions on a single semiconductor wafer so that it is integrated monolithically without any external device or semiconductor materials. The thyristor can be switching on and off optically by two discrete light beams illuminated on separated openings of electrodes on the top surface of a semiconductor body. The carrier injection of the turning on process is achieved by illuminating the bulk of the thyristor with a high level light through the first aperture over the cathode to create high density charge carriers serving as the gate current injection and to electrically short the emitter and drift layer.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: November 2, 2010
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Yeuan-Ming Sheu
  • Patent number: 7705368
    Abstract: An insulated gate type thyristor includes: a first current terminal semiconductor region of a first conductivity type having a high impurity concentration; a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a low impurity concentration and formed on the first current terminal semiconductor region; a second base semiconductor region of the first conductivity type having a low impurity concentration and formed on the first base semiconductor region; a second current terminal semiconductor region of the second conductivity type having a high impurity concentration and formed on the second base semiconductor region; a trench passing through the second current terminal semiconductor region and entering the second base semiconductor region leaving some depth thereof, along a direction from a surface of the second current terminal semiconductor region toward the first base semiconductor region; and an insulated gate electrode structure formed in the trench.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 27, 2010
    Assignee: Fujifilm Corporation
    Inventors: Vladimir Rodov, Hidenori Akiyama
  • Patent number: 7687826
    Abstract: A main thyristor (1) has a recovery protection which is integrated into a drive thyristor (2) whose n-doped emitter (25) is electrically connected to a main thyristor control terminal (140). Moreover, the p-doped emitter (28) of the drive thyristor (2) is electrically connected to the p-doped emitter (18) of the main thyristor (1). Various optional measures for realizing a recovery protection are provided in this case. A method for producing a thyristor system having a main thyristor and a drive thyristor, the drive thyristor (2) having anode short circuits (211) involves introducing particles (230) into a target region (225) of the semiconductor body (200) of the drive thyristor (2), the distance between the target region (225) and a front side (201) of the semiconductor body (200) opposite to the rear side (202) being less than or equal to the distance between the p-doped emitter (28) and the front side (201).
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: March 30, 2010
    Inventors: Hans-Joachim Schulze, Franz Josef Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
  • Patent number: 7633095
    Abstract: Integrating high-voltage devices with other circuitry, which may be fabricated on a semiconductor wafer using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, and the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The high-voltage devices may be used to create useful high-voltage circuits, such as level-shifting circuits, input protection circuits, charge pump circuits, switching circuits, latch circuits, latching switch circuits, interface circuits, any combination thereof, or the like. The high-voltage circuits may be controlled by the other circuitry.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: December 15, 2009
    Assignee: RF Micro Devices, Inc.
    Inventors: Daniel Charles Kerr, David C. Dening, Julio Costa
  • Patent number: 7339203
    Abstract: A thyristor and a method for manufacturing the thyristor that includes a gate region extending from the first major surface into a semiconductor substrate and an anode region extending from the second major surface into the semiconductor substrate. A cathode region extends into a portion of the gate region. Optionally, enhanced doped regions extend into the gate and anode regions. A mesa structure having a height HG is formed from the first major surface and a mesa structure having a height HA is formed from the second major surface. The gate region extends under the first major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HG. The anode region extends under the second major surface of the semiconductor substrate and it extends vertically into the semiconductor substrate a distance that is greater than height HA.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: March 4, 2008
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Emmanuel Saucedo-Flores, David M. Culbertson
  • Patent number: 7276778
    Abstract: A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 2, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Koh Yoshikawa
  • Patent number: 7262442
    Abstract: A triac including on its front surface side an autonomous starting well of the first conductivity type containing a region of the second conductivity type arranged to divide it, in top view, into a first and a second well portion, the first portion being connected to a control terminal and the second portion being connected with said region to the main front surface terminal.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: August 28, 2007
    Assignee: STMicroelectronics S.A.
    Inventor: Samuel Menard
  • Patent number: 7262443
    Abstract: Method and apparatus for forming a semiconductor device. The method includes defining a plurality of rows in a semiconductor layer. Thereafter, on one or more of the plurality of rows, one or more bipolar junction devices are formed. Each of the bipolar junction devices has a first end region and a second end region. A quantity of a pre-amorphization ion is then implanted into at least one of the first end region and the second end region of a bipolar junction device for example. A silicide is formed in the semiconductor layer at the first end region and the second end region having implanted therein the quantity of the pre-amorphization ion. Additionally, laterally extending upper edges of the plurality of rows forming corners may be rounded prior to the implantation of the pre-amorphization.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: August 28, 2007
    Assignee: T-Ram Semiconductor Inc.
    Inventor: Kevin J. Yang
  • Patent number: 7242036
    Abstract: A semiconductor element includes a first semiconductor layer of a first conductivity type including a non-deposition region and a deposition region. The first semiconductor layer has a first upper surface on the non-deposition region. The semiconductor element also includes a second semiconductor layer of a second conductivity type on the deposition region of the first semiconductor layer. The second semiconductor layer has a second upper surface. The semiconductor element includes first and second electrode layers on the first and second semiconductor layers, respectively, which define an inclined surface for continuous connection therebetween. The semiconductor element includes an insulating layer on the inclined surface, spaced from at least either one of the first and second electrode layers. At least either one of the first and second semiconductor layers includes a recessed portion between the respective one of the first and second electrode layers and the insulating layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 10, 2007
    Assignee: Mitsubishi Electric Corporation
    Inventor: Nobuhisa Nakashima