Abstract: A multi-level memory cell having a bottom electrode, a first dielectric layer, a plurality of memory material layers, a plurality of second dielectric layers, and an upper electrode is provided. The bottom electrode is disposed in a substrate. The first dielectric layer is disposed on the substrate and has an opening exposing the bottom electrode. The memory material layers are stacked on a sidewall of the first dielectric layer exposed by the opening and are electrically connected to the bottom electrode. The second dielectric layers are respectively disposed between every adjacent two memory material layers and are located on the sidewall of the first dielectric layer. The upper electrode is disposed on the memory material layers. A manufacturing method of the multi-level memory cell is further provided. A multi-bit data can be stored in a single memory cell, and both the process complexity and the cost are reduced.

Abstract: A photodiode includes a p-type semiconductor material and an n-type chalcogenide compound. The p-type semiconductor material and the n-type chalcogenide compound form a pn-junction.

Abstract: A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.

Abstract: A multi-level memory cell having a bottom electrode, a first dielectric layer, a plurality of memory material layers, a plurality of second dielectric layers, and an upper electrode is provided. The bottom electrode is disposed in a substrate. The first dielectric layer is disposed on the substrate and has an opening exposing the bottom electrode. The memory material layers are stacked on a sidewall of the first dielectric layer exposed by the opening and are electrically connected to the bottom electrode. The second dielectric layers are respectively disposed between every adjacent two memory material layers and are located on the sidewall of the first dielectric layer. The upper electrode is disposed on the memory material layers. A manufacturing method of the multi-level memory cell is further provided. A multi-bit data can be stored in a single memory cell, and both the process complexity and the cost are reduced.

Abstract: The present invention is generally directed to a bulk barium copper sulfur fluoride (BCSF) material made by combining Cu2S, BaS and BaF2, heating the ampoule between 400 and 550 ° C. for at least two hours, and then heating the ampoule at a temperature between 550 and 950 ° C. for at least two hours. The BCSF material may be doped with potassium, rubidium, or sodium. The present invention also provides for a BCSF transparent conductive thin film made by forming a sputter target by either hot pressing bulk BCSF or hot pressing Cu2S, BaS and BaF2 powders and sputtering a BCSF thin film from the target onto a substrate. The present invention is further directed to a p-type transparent conductive material comprising a thin film of BCSF on a substrate where the film has a conductivity of at least 1 S/cm. The substrate may be a plastic substrate, such as a polyethersulfone, polyethylene terephthalate, polyimide, or some other suitable plastic or polymeric substrate.

Abstract: A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate.

Abstract: The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

Abstract: A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.