Abstract: Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide hand-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range.

Abstract: High power insulated gate bipolar junction transistors are provided that include a wide band gap semiconductor bipolar junction transistor (“BJT”) and a wide band gap semiconductor MOSFET that is configured to provide a current to the base of the BJT. These devices further include a minority carrier diversion semiconductor layer on the base of the BJT and coupled to the emitter of the BJT, the minority carrier diversion semiconductor layer having a conductivity type opposite the conductivity type of the base of the BJT and forming a heterojunction with the base of the BJT.

Abstract: An original wafer, typically silicon, has the form of a desired end PV wafer. The original may be made by rapid solidification or CVD. It has small grains. It is encapsulated in a clean thin film, which contains and protects the silicon when recrystallized to create a larger grain structure. The capsule can be made by heating a wafer in the presence of oxygen, or steam, resulting in silicon dioxide on the outer surface, typically 1-2 microns. Further heating creates a molten zone in space, through which the wafer travels, resulting in recrystallization with a larger grain size. The capsule contains the molten material during recrystallization, and protects against impurities. Recrystallization may be in air. Thermal transfer through backing plates minimizes stresses and defects. After recrystallization, the capsule is removed.

Abstract: A semiconductor device includes: a semiconductor layer including silicon carbide, which has been formed on a substrate; a semiconductor region 15 of a first conductivity type defined on the surface of the semiconductor layer 10; a semiconductor region 14 of a second conductivity type, which is defined on the surface 10s of the semiconductor layer so as to surround the semiconductor region 15 of the first conductivity type; and a conductor 19 with a conductive surface 19s that contacts with the semiconductor regions 15 and 14 of the first and second conductivity types. On the surface 10s of the semiconductor layer, the semiconductor region 15 of the first conductivity type has at least one first strip portion 60 that runs along a first axis i. The width C1 of the semiconductor region 15 of the first conductivity type as measured along the first axis i is greater than the width A1 of the conductive surface 19s as measured along the first axis i.

Abstract: The invention provides a high-quality SiC single-crystal substrate, a seed crystal for producing the high-quality SiC single-crystal substrate, and a method of producing the high-quality SiC single-crystal substrate, which enable improvement of device yield and stability. Provided is an SiC single-crystal substrate wherein, when the SiC single-crystal substrate is divided into 5-mm square regions, such regions in which dislocation pairs or dislocation rows having intervals between their dislocation end positions of 5 ?m or less are present among the dislocations that have ends at the substrate surface account for 50% or less of all such regions within the substrate surface and the dislocation density in the substrate of dislocations other than the dislocation pairs or dislocation is 8,000/cm2.

Abstract: An SiC semiconductor device is provided, which comprises: a substrate made of silicon carbide and having a principal surface; a drift layer made of silicon carbide and disposed on the principal surface; an insulating layer disposed on the drift layer and including an opening; a Schottky electrode contacting with the drift layer through the opening; a termination structure disposed around an outer periphery of the opening; and second conductivity type layers disposed in a surface part of the drift layer, contacting the Schottky electrode, surrounded by the termination structure, and separated from one another. The second conductivity type layers include a center member and ring members. Each ring member surrounds the center member and is arranged substantially in a point symmetric manner with respect to the center member.

Abstract: The present invention provides a single-crystal silicon carbide ingot capable of providing a good-quality substrate low in dislocation defects, and a substrate and epitaxial wafer obtained therefrom. It is a single-crystal silicon carbide ingot comprising single-crystal silicon carbide which contains donor-type impurity at a concentration of 2×1018 cm?3 to 6×1020 cm3 and acceptor-type impurity at a concentration of 1×1018 cm?3 to 5.99×1020 cm?3 and wherein the concentration of the donor-type impurity is greater than the concentration of the acceptor-type impurity and the difference is 1×1018 cm?3 to 5.99×1020 cm?3, and a substrate and epitaxial wafer obtained therefrom.

Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm?2.

Abstract: An electronic device includes a wide bandgap thyristor having an anode, a cathode, and a gate terminal, and a wide bandgap bipolar transistor having a base, a collector, and an emitter terminal. The emitter terminal of the bipolar transistor is directly coupled to the anode terminal of the thyristor such that the bipolar transistor and the thyristor are connected in series. The bipolar transistor and the thyristor define a wide bandgap bipolar power switching device that is configured to switch between a nonconducting state and a conducting state that allows current flow between a first main terminal corresponding to the collector terminal of the bipolar transistor and a second main terminal corresponding to the cathode terminal of the thyristor responsive to application of a first control signal to the base terminal of the bipolar transistor and responsive to application of a second control signal to the gate terminal of the thyristor. Related control circuits are also discussed.

Abstract: In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes applying a dielectric layer to a surface, applying a metal layer to the dielectric layer, and adding a cap layer on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack such that an electrode of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal.

Abstract: An optically-controlled power switch for use as an electrical switch is generally provided. The device can include a wide bandgap semiconducting material defining a stack having a p-n junction, a metal mask overlying the top surface of the stack and defining at least one opening to allow light to pass through the metal mask; a first lead wire connected to the metal stack; and a second lead wire connected to the bottom surface of the stack.

Abstract: LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.

Abstract: A chip scale package (CSP) semiconductor device can include a semiconductor layer, circuitry on an active surface of the semiconductor layer, and a diamond layer on a back side of the semiconductor layer. The diamond layer can provide an efficient heat sink for the semiconductor layer, with a thermal conductivity which can be more than three times greater than the thermal conductivity of copper. Further, a hardness of the diamond layer (up to about 10 times stronger than silicon) can provide effective protection against damage to the exposed semiconductor layer, for example during manufacturing, handling, and use of the CSP device. Thus a thin protective diamond layer can be used, which can result in a very thin CSP package design.

Abstract: A cubic silicon carbide single crystal thin film is manufactured by a method. A sacrificial layer is formed on a surface of a substrate. A cubic semiconductor layer is formed on the sacrificial layer, the cubic semiconductor layer having at least a surface of cubic crystal structure. A cubic silicon carbide single crystal layer is formed on the cubic semiconductor layer. The sacrificial layer is etched away to release a multilayer structure of the cubic semiconductor layer and the 3C—SiC layer from the substrate. A cubic silicon carbide single crystal thin film of a multilayer structure includes an AlxGa1-xAs (0.6>×?0) layer and a cubic silicon carbide single crystal layer. A metal layer is formed on a substrate. The multilayer structure is bonded to the metal layer with the AlxGa1-xAs (0.6>×?0) in direct contact with the metal layer.

Abstract: A method for manufacturing a semiconductor thin film device includes: forming a buffer layer on an Si (111) substrate and a single crystal semiconductor layer on the buffer layer; forming an island including the semiconductor layer, buffer layer, and a portion of the substrate; forming a coating layer on the island; etching the substrate along its Si (111) plane to release the island from the substrate, the coating layer serving as a mask; and bonding the released island to another substrate, a released surface of the released island contacting the another substrate. A semiconductor device includes a single crystal semiconductor layer other than Si, which has a semiconductor device formed on a front surface of an Si (111) layer lying in a (111) plane. The layer is bonded to another substrate with a back surface contacting the another substrate or a bonding layer formed on the another substrate.

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.

Abstract: Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer.

Abstract: A semiconductor device having a JBS diode includes: a SiC substrate; a drift layer on the substrate; an insulation film on the drift layer having an opening in a cell region; a Schottky barrier diode having a Schottky electrode contacting the drift layer through the opening and an ohmic electrode on the substrate; a terminal structure having a RESURF layer in the drift layer surrounding the cell region; and multiple second conductive type layers in the drift layer on an inner side of the RESURF layer contacting the Schottky electrode. The second conductive type layers are separated from each other. The second conductive type layers and the drift layer provide a PN diode. Each second conductive type layer has a depth larger than the RESURF layer.

Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; an epitaxial region having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the epitaxial region comprises an impurity of a first conductivity type; a first portion of the semiconductor substrate adjoining the epitaxial region, wherein the first portion of the semiconductor substrate is of the first conductivity type; and a second portion of the semiconductor substrate adjoining the first portion. The second portion of the semiconductor substrate is of a second conductivity type opposite the first conductivity type. A silicide region is formed on the epitaxial region and the first and the second portions of the semiconductor substrate.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: An objective is to provide a manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the manufacturing method increase of the manufacturing cost can also be prevented as much as possible. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch<Lg<Lwell is satisfied; and the channel regions are further formed by diffusing by activation annealing boron as a third impurity, having been implanted by activation annealing into the source regions, into a silicon carbide layer.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: A single crystal SiC substrate is produced with low cost in which a polycrystalline SiC substrate with relatively low cost is used as a base material substrate where the single crystal SiC substrate has less strain, good crystallinity and large size. The method including a P-type ion introduction step for implanting P-type ions from a side of a surface Si layer 3 into an SOI substrate 1 in which the surface Si layer 3 and an embedded oxide layer 4 having a predetermined thickness are foamed on an Si base material layer 2 to convert the embedded oxide layer 4 into a PSG layer 6 to lower a softening point, and an SiC forming step for heating the SOI substrate 1 having the PSG layer 6 formed therein in an atmosphere of hydrocarbon-based gas to convert the surface Si layer 3 into SiC, and thereafter, cooling the resulting substrate to foam a single crystal SiC layer 5 on a surface thereof.

Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.

Abstract: A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (1) including a silicon carbide layer (2); a high-concentration impurity region (4) provided in the silicon carbide layer (2); an ohmic electrode (9) electrically connected with the high-concentration impurity region (4); a channel region electrically connected with the high-concentration impurity region; a gate insulating layer (14) provided on the channel region; and a gate electrode (7) provided on the gate insulating layer (14). The ohmic electrode (9) contains an alloy of titanium, silicon and carbon, and the gate electrode (7) contains titanium silicide.

Abstract: An object is to realize an integrated circuit included in a semiconductor device which has multiple functions, or to increase the size of an integrated circuit even when the integrated circuit is formed using a silicon carbide substrate. The integrated circuit includes a first transistor including an island-shaped silicon carbide layer provided over a substrate with a first insulating layer interposed therebetween, a first gate insulating layer provided over the silicon carbide layer, and a first conductive layer provided over the first gate insulating layer and overlapped with the silicon carbide layer; and a second transistor including an island-shaped single crystal silicon layer provided over the substrate with a second insulating layer interposed therebetween, a second gate insulating layer provided over the single crystal silicon layer, and a second conductive layer provided over the second gate insulating layer and overlapped with the single crystal silicon layer.

Abstract: A semiconductor device which is capable of operating at an operation frequency “f”, includes a substrate, a first element unit and a second element unit. The substrate has a thermal diffusion coefficient “D”. The first element unit is formed on the substrate. The first element includes a first active element. The second element unit is adjacent to the first element unit on the substrate. The second element includes a second active element. The second active element acts on a different timing from the first active element. Moreover, a distance of between a first gravity center of the first element unit and a second gravity center of the second element unit is equal to or less than twice of a thermal diffusion length (D/?f)1/2.

Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.

Abstract: An electronic device includes a silicon carbide layer having a first conductivity type and having a first surface and a second surface opposite the first surface, and first and second silicon carbide Zener diodes on the silicon carbide layer. Each of the first and second silicon carbide Zener diodes may include a first heavily doped silicon carbide region having a second conductivity type opposite the first conductivity type on the silicon carbide layer, and an ohmic contact on the first heavily doped silicon carbide region.

Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A first conductive type impurity is diffused in the silicon carbide substrate. A method of producing a semiconductor device includes preparing the silicon carbide substrate forming a first conductive type impurity diffused region on the first main surface therein; preparing a silicon substrate having a third main surface and a fourth main surface opposite to the third main surface, said silicon substrate including a thermal oxidation film formed on the third main surface; and attaching the third main surface to the first main surface via the thermal oxidation film.

Abstract: A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.

Abstract: A channel layer (40) for forming a portion of a carrier path between a source electrode (100) and a drain electrode (110) is formed on a drift layer (30). The channel layer (40) includes Ge granular crystals formed on the drift layer (30), and a cap layer covering the Ge granular crystals.

Abstract: A second trench in each source electrode portion (Schottky diode portion) is formed to have a depth equal to or larger than the depth of a first trench in each gate electrode portion. The distance between the first and second trenches is set to be not longer than 10 ?m. A source electrode is formed in the second trench and a Schottky junction is formed in the bottom portion of the second trench. In this manner, it is possible to provide a wide band gap semiconductor device which is small-sized, which has low on-resistance and low loss characteristic, in which electric field concentration into a gate insulating film is relaxed to suppress reduction of a withstand voltage, and which has high avalanche breakdown tolerance at turn-off time.

Abstract: LED devices incorporating diamond materials and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.

Abstract: At least part of a semiconductor layer or a semiconductor substrate includes a semiconductor region having a large energy gap. The semiconductor region having a large energy gap is preferably formed from silicon carbide and is provided in a position at least overlapping with a gate electrode provided with an insulating layer between the semiconductor region and the gate electrode. By making a structure in which the semiconductor region is included in a channel formation region, a dielectric breakdown voltage is improved.

Abstract: A MOSFET driver compatible JFET device is disclosed. The JFET device can include a gate contact, a drain contact, and a source contact. The JFET device can further include a first gate region of semiconductor material adjacent the gate contact and a second region of semiconductor material adjacent the first gate region. The first gate region and the second gate region can form a first p-n junction between the first gate region and the second gate region. The JFET device can further include a channel region of semiconductor material adjacent the source contact. The channel region and the second gate region can form a second p-n junction between the second gate region and the channel region.

Abstract: A semiconductor device according to the present invention includes: a silicon carbide substrate (11) that has a principal surface and a back surface; a semiconductor layer (12), which has been formed on the principal surface of the silicon carbide substrate; and a back surface ohmic electrode layer (1d), which has been formed on the back surface of the silicon carbide substrate. The back surface ohmic electrode layer (1d) includes: a reaction layer (1da), which is located closer to the back surface of the silicon carbide substrate and which includes titanium, silicon and carbon; and a titanium nitride layer (1db), which is located more distant from the back surface of the silicon carbide substrate.

Abstract: A direction of a dislocation line of a threading dislocation is aligned, and an angle between the direction of the dislocation line of the threading dislocation and a [0001]-orientation c-axis is equal to or smaller than 22.5 degrees. The threading dislocation having the dislocation line along with the [0001]-orientation c-axis is perpendicular to a direction of a dislocation line of a basal plane dislocation. Accordingly, the dislocation does not provide an extended dislocation on the c-face, so that a stacking fault is not generated. Thus, when an electric device is formed in a SiC single crystal substrate having the direction of the dislocation line of the threading dislocation, which is the [0001]-orientation c-axis, a SiC semiconductor device is obtained such that device characteristics are excellent without deterioration, and a manufacturing yield ration is improved.

Abstract: A semiconductor device is fabricated on an off-cut semiconductor substrate 11. Each unit cell 10 thereof includes: a first semiconductor layer 12 on the surface of the substrate 11; a second semiconductor layer 16 stacked on the first semiconductor layer 12 to have an opening 16e that exposes first and second conductive regions 15 and 14 at least partially; a first conductor 19 located inside the opening 16e of the second semiconductor layer 16 and having a conductive surface 19s that contacts with the first and second conductive regions 15 and 14; and a second conductor 17 arranged on the second semiconductor layer 16 and having an opening 18e corresponding to the opening 16s of the second semiconductor layer 16.

Abstract: The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.

Abstract: The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.

Abstract: Silicon carbide semiconductor device includes trench, in which connecting trench section is connected to straight trench section. Straight trench section includes first straight trench and second straight trench extending in parallel to each other. Connecting trench section includes first connecting trench perpendicular to straight trench section, second connecting trench that connects first straight trench and first connecting trench to each other, and third connecting trench that connects second straight trench and first connecting trench to each other. Second connecting trench extends at 30 degrees of angle with the extension of first straight trench. Third connecting trench extends at 30 degrees of angle with the extension of second straight trench. A manufacturing method according to the invention for manufacturing a silicon carbide semiconductor device facilitates preventing defects from being causes in a silicon carbide semiconductor device during the manufacture thereof.

Abstract: A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the silicon carbide layer and the silicon substrate to connect to both of them. The semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate. The current flows through the conductive layer.

Abstract: In a SiC pn diode, the lifetime is controlled by electron beam irradiation of about 3×1013 cm?2 or more. As a result of the life time control, as shown by a current-voltage characteristic (K10) in FIG. 1, the current started to flow at about 32 V and the on-voltage at an applied current of 100 A was 50 V in the SiC pn diode. In this case, the SiC pn diode has a resistance of 0.5? when the SiC pn diode is turned on. The conducting region of the SiC pn diode is 0.4 cm2, and is reduced to 0.2 ?cm2 by increasing the on-resistance by the lifetime control. Therefore, for instance, in an electric circuit device using a diode and a resistor connected in series in prior arts, the resistor can be eliminated.

Abstract: An SiC substrate includes the steps of preparing a base substrate having a main surface and made of SiC, washing the main surface using a first alkaline solution, and washing the main surface using a second alkaline solution after the step of washing with the first alkaline solution. The SiC substrate has the main surface, and an average of residues on the main surface are equal to or larger than 0.2 and smaller than 200 in number.

Abstract: Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.

Abstract: An embodiment of a process for manufacturing an electronic device on a semiconductor body of a material with wide forbidden bandgap having a first conductivity type.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.