Abstract: A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.

Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

Abstract: Closed loop control may be used to improve uniformity of contact or via critical dimension using chemical mechanical planarization. For example, real-time closed loop control may be used to adjust oxide buffing or over-polishing time in a chemical mechanical planarization process to more uniformly and consistently achieve a target critical dimension of a semiconductor wafer.

Abstract: A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.

Abstract: A cast silicon crystalline ingot comprises two major generally parallel surfaces, one of which is the front surface and the other of which is the back surface; a perimeter surface connecting the front surface and the back surface; and a bulk region between the front surface and the back surface; wherein the cast silicon crystalline ingot has no transverse dimension less than about five centimeters; the cast silicon crystalline ingot has a dislocation density of less than 1000 dislocations/cm2. Wafers sliced from the cast silicon crystalline ingot have solar cell efficiency of at least 17.5% and light induced degradation no greater than 0.2%.

Abstract: A method of balancing a microelectromechanical system comprises determining if a microelectromechanical system is balanced in a plurality of orthogonal dimensions, and if the microelectromechanical system is not balanced, selectively depositing a first volume of jettable material on a portion of the microelectromechanical system to balance the microelectromechanical system in the plurality of orthogonal dimensions. A jettable material for balancing a microelectromechanical system comprises a vehicle, and a dispersion of nano-particles within the vehicle, in which the total mass of jettable material deposited on the microelectromechanical system is equal to the weight percentage of nano-particles dispersed within the vehicle multiplied by the mass of jettable material deposited on the microelectromechanical system.

Abstract: A method of dicing a semiconductor wafer includes forming a layer stack on a first main surface of a substrate. The layer stack and a portion of the substrate are etched according to a pattern defining an intended dicing location to obtain a trench structure. The substrate is irradiated with a laser beam to locally modify the substrate between a bottom of the trench structure and a second main surface of the substrate opposite to the first main surface.

Abstract: The present invention relates to a process for smoothing the surface of a semiconductor wafer by fusion. The process includes defining a reference length which dimensions wafer surface roughness that is to be reduced or removed, and scanning the surface with a fusion beam while adjusting parameters of the fusion beam so as to fuse, during the scanning of the surface, a local surface zone of the wafer whose length is greater than or equal to the reference length, with the scanning continued to smooth the entire surface of the wafer by eliminating surface roughnesses of period lower than the reference length. The present invention also relates to a semiconductor wafer having a surface layer made of a semiconducting material that is smoothed by the process and that does not exhibit any roughness of period lower than the reference length.

Abstract: The instant disclosure relates to a nanostructuring process for an ingot surface prior to the slicing operation. A surface treatment step is performed for at least one surface of the ingot in forming a nanostructure layer thereon. The nanostructure layer is capable of enhancing the mechanical strength of the ingot surface to reduce the chipping ratio of the wafer during slicing.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: (a) forming cutting grooves in an element formation surface of a semiconductor wafer on which semiconductor elements are formed; (b) applying a protection tape on the element formation surface of the semiconductor wafer; (c) grinding a rear surface of the semiconductor wafer to thin the semiconductor wafer and to divide the semiconductor wafer into a plurality of semiconductor chips on which the semiconductor elements are formed; (d) forming an adhesive layer on the rear surface of the semiconductor wafer; (e) separating and cutting the adhesive layer for each of the semiconductor chips; and (f) removing the protection tape. The (e) is performed by spraying a high-pressure air to the adhesive layer formed on the rear surface of the semiconductor wafer while melting or softening the adhesive layer by heating.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

Abstract: An etching liquid for texturing a silicon wafer surface is provided. The etching liquid may include an aqueous solution of at least one alkaline etching agent and at least one polysaccharide or derivative thereof. Also provided is a process for texture etching a silicon wafer using the etching liquid of the invention.

Abstract: A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.

Abstract: A method of drying a surface of a substrate is provided. The method includes supporting a substrate; rotating the substrate about a rotational center point; applying a liquid to the substrate via a liquid dispenser; applying a drying fluid to the substrate via a drying fluid dispenser; moving the drying fluid dispenser and the liquid dispenser in a direction toward an edge region of the substrate, the drying fluid being applied closer to the rotational center point than the fluid; upon the liquid being applied to the edge region of the substrate, discontinuing application of the liquid while continuing the manipulation of the drying fluid dispenser; and upon the drying fluid being applied to the edge region of the substrate, continuing to apply the drying fluid for a predetermined period of time.

Abstract: A SOI substrate includes a silicon substrate, a silicon oxide layer arranged on the silicon substrate, a silicon layer arranged on the silicon oxide layer, a gettering layer arranged in the silicon substrate, and a damaged layer formed of an impurity-doped region arranged in the silicon oxide layer.

Abstract: Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.

Abstract: A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size.

Abstract: An annealed wafer obtained by performing rapid thermal annealing on a silicon single crystal wafer sliced from a silicon single crystal ingot in which an entire plane is an OSF region, an N region outside an OSF region, or a mixed region thereof, the silicon single crystal ingot being grown by the Czochralski method, in which RIE defects do not exist in a region having at least a depth of 1 ?m from a surface, a good chip yield of a TDDB characteristic is 80% or more, and a depth of a region where an oxygen concentration is decreased due to outward diffusion is within 3 ?m from the surface, and a method for producing an annealed wafer.

Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.

Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.

Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 ?m at edges of wafers.

Abstract: Methods for texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells. Texturizing of the wafer surface is carried out with a TMAH based solution. The texturizing solution may further include isopropyl alcohol and ethylene glycol at different dilutions in DI water to further improves results.

Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.

Abstract: A method for producing a semiconductor wafer includes pulling a single crystal of semiconductor material, slicing a semiconductor wafer from the single crystal and polishing the semiconductor wafer with the polishing pad and polishing agent. The polishing agent is free of solid materials having abrasive action and the polishing pad contains fixedly bonded solid materials with abrasive action. During polishing the polishing agent is supplied in a gap between the semiconductor wafer and polishing pad. The polishing agent has a pH value in a range of 9.5 to 12.5.

Abstract: The present invention is related to a supporting substrate for manufacturing vertically-structured semiconductor light emitting device and a vertically-structured semiconductor light emitting device using the same, which minimize damage and breaking of a multi-layered light-emitting structure thin film separated from a sapphire substrate during the manufacturing process, thereby improving the whole performance of the semiconductor light emitting device.

Abstract: Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.

Abstract: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.

Abstract: A wafer includes a wafer frontside and a region adjacent to the device surface, wherein the region includes vacancy-oxygen complexes and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property.

Abstract: A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms.

Abstract: The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.

Abstract: The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that includes an open portion reaching the silicon wafer and having an aspect ratio of ?3/3 or more; a seed compound semiconductor crystal that is formed in the open portion and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface.

Abstract: Provided is a method for manufacturing a silicon epitaxial wafer by growing an epitaxial layer by placing a silicon substrate on a susceptor. The method includes at least a step of forming a silicon oxide film entirely on the rear surface of the silicon substrate; a step of removing the silicon oxide film formed at least on an edge section of the silicon substrate; and a step of placing the silicon substrate on the susceptor with the silicon oxide film in between. An epitaxial layer is grown on the silicon substrate, while holding the silicon substrate by the susceptor with the silicon oxide film in between. Thus, the silicon epitaxial wafer by which generation of particles can be reduced in a device manufacturing process and a method for manufacturing such silicon epitaxial wafer are provided.

Abstract: Semiconductor wafers are produced by a process of: a) providing a semiconductor wafer by cutting a silicon ingot into wafers; b) rounding the edge of the wafer, so that the wafer comprises plane surfaces on the frontside and backside and rounded oblique surfaces in the edge region; c) polishing the frontside and backside of the wafer, the frontside being polished by chemical-mechanical polishing using a polishing pad which is free of abrasive fixed in the polishing pad; backside polishing being carried out in three steps, using a polishing pad containing fixed abrasive which is pressed onto the backside of the wafer, a polishing agent free of solids introduced between the polishing pad and the backside of the wafer in the first step, a polishing agent containing abrasive being introduced in the second and third steps, a polishing pressure of 8-15 psi in the first and second steps being reduced to 0.5-5 psi in the third step.

Abstract: A lateral power semiconductor device has a substrate and an isolation layer formed over the substrate for reducing minority carrier storage in the substrate. A well region is formed over the isolation layer. A source region, drain region, and channel region are formed in the well. A first region is formed on a surface of the lateral power semiconductor device adjacent to the source region. The lateral power semiconductor device has a body diode between the first region and drain region. The isolation layer confines the minority carrier charge from the body diode to a depth of less than 20 ?m from the surface of the lateral power semiconductor device. In one embodiment, the isolation layer is a buried oxide layer and the substrate is an n-type or p-type handle wafer. Alternatively, the isolation layer is an epitaxial layer and the substrate is made with N+ or P+ semiconductor material.

Abstract: A Cu—Mo substrate 10 according to the present invention includes: a Cu base 1 containing Cu as a main component; an Mo base having opposing first and second principal faces 2a, 2b and containing Mo as a main component, the second principal face 2b of the Mo base 2 being positioned on at least a portion of a principal face 1a of the Cu base 1; and a first Sn—Cu-type alloy layer 3 covering the first principal face 2a and side faces 2c and 2d of the Mo base 2, the first Sn—Cu-type alloy layer 3 containing no less than 1 mass % and no more than 13 mass % of Sn.

Abstract: A silicon substrate with periodical structure is disclosed, which comprises: a silicon substrate, and at least one periodical structure formed on at least one surface of the silicon substrate and having plural micro-cavities; wherein, the micro-cavities are arranged in an array, the micro-cavities are each in an inverted awl-shape or an inverted truncated cone-shape, the length of the base line of the micro-cavities in the inverted awl-shape is 100˜2400 nm, the diameter of the micro-cavities in the inverted truncated cone-shape is 100˜2400 nm, and the depth of the micro-cavities is 100˜2400 nm.

Abstract: A sapphire substrate with periodical structure is disclosed, which comprises: a sapphire substrate, and at least one periodical structure formed on at least one surface of the sapphire substrate and having plural micro-cavities; wherein, the micro-cavities are arranged in an array, the micro-cavities are each in an inverted awl-shape, the length of the base line of the micro-cavities is 100˜2400 nm, and the depth of the micro-cavities is 25˜1000 nm.

Abstract: In a crystal growth reactor, a source material having an etching action and a crystal growth source material are simultaneously supplied to a semiconductor wafer surface, so that residual impurities can be eliminated in an efficient manner by balancing etching rate and crystal growth rate.

Abstract: An epitaxial wafer is provided capable of eliminating particles in a device process, particles being generated from scratches in a boundary area between a rear surface and a chamfered surface of a wafer. The number of scratches in the boundary area between the rear surface and the chamfered surface is small, and thus the number of particles generated from the scratches is reduced at a time of immersion in an etching solution in the device process. Thereby, a device yield is increased.

Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.

Abstract: In a chamber of a plasma processing apparatus, a cathode electrode and an anode electrode are disposed at a distance from each other. The cathode electrode is supplied with electric power from an electric power supply portion. The anode electrode is electrically grounded and a substrate is placed thereon. The anode electrode contains a heater. In an upper wall portion of the chamber, an exhaust port is provided and connected to a vacuum pump through an exhaust pipe. In a lower wall portion of a wall surface of the chamber, a gas introduction port is provided. A gas supply portion is provided outside the chamber.

Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

Abstract: The present invention relates to a method of treating wafers comprising at least one surface layer of silicon-germanium (SiGe) and a layer of strained silicon (sSi) in contact with the SiGe layer, the sSi layer being exposed by etching of the SiGe layer, the method comprising the steps of: (a) a first selective etch of the SiGe layer, optionally followed by an oxidative cleaning step; (b) a rinsing step using deionized water; (c) drying; and (d) a second selective etch step. The present invention relates to a wafer comprising at least one surface layer of strained silicon (sSi), said surface layer of sSi having a thickness of at least 5 nanometres and at most 100 ?m of at most 200 defects per wafer.

Abstract: A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.

Abstract: A SOI substrate includes a silicon substrate, a silicon oxide layer arranged on the silicon substrate, a silicon layer arranged on the silicon oxide layer, a gettering layer arranged in the silicon substrate, and a damaged layer formed of an impurity-doped region arranged in the silicon oxide layer.

Abstract: A method of manufacturing a semiconductor device includes providing first and second semiconductor substrates, each having first and second main surfaces opposite to one another. A roughened surface is formed on at least one of the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate. A dielectric layer is formed on the first main surface of the semiconductor substrate and the second semiconductor substrate is disposed on the dielectric layer opposite to the first semiconductor substrate. The second main surface of the second semiconductor substrate contacts the dielectric layer.

Abstract: Semiconductor wafers composed of monocrystalline silicon and doped with nitrogen contain an OSF region and a PV region, wherein the OSF region extends from the center radially toward the edge of the wafer as far as the Pv region; the wafer has an OSF density of less than 10 cm?2, a BMD density in the bulk of at least 3.5×108 cm?3, and a radial distribution of the BMD density with a fluctuation range BMDmax/BMDmim of not more than 3. The wafers are produced by controlling initial nitrogen content and maintaining oxygen within a narrow window, followed by a heat treatment.

Abstract: A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×1017 atoms/cm3, slicing a wafer from the silicon ingot after doping the silicon ingot with phosphorus, forming a polysilicon layer or a strained layer on one main surface of the wafer, mirror polishing the other main surface of the wafer, and performing a heat treatment for the wafer in a non-oxidizing atmosphere.

Abstract: When positively charged ions are implanted into a target substrate, charge-up damage may occur on the target substrate. In order to suppress charge-up caused by secondary electrons emitted from the target substrate when positively charged ions are implanted, a conductive member is installed at a position facing the target substrate and electrically grounded with respect to a high frequency. Further, a field intensity generated in the target substrate may be reduced by controlling an RF power applied to the target substrate in pulse mode.

Abstract: The present invention provides a manufacturing method of a high performance active matrix substrate at a high throughput with a less expensive apparatus, and an image display device using the active matrix substrate. On a stage moving in the short axis direction X and long axis direction Y on a rail, a glass substrate is carried, which has an amorphous silicon semiconductor film formed. Polycrystallized and large grain silicon film may be obtained by intensity modulating the pulsed laser beam in a line beam shape by means of a phase shift mask with a periodicity in the long axis direction Y of the laser beam, moving the laser beam randomly in the modulation direction of the amorphous silicon semiconductor film formed on the glass substrate to expose to crystallize the film. The image display device may incorporate an active matrix substrate having active elements such as thin film transistors formed by this silicon film.