Abstract: An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n? epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.

Abstract: A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator.

Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.

Abstract: A method for manufacturing array substrate with embedded photovoltaic cell includes: providing a substrate; forming a buffer layer on the substrate; forming an amorphous silicon layer on the buffer layer; converting the amorphous silicon layer into a polysilicon layer; forming a pattern on the polysilicon layer; forming a first photoresist pattern on the polysilicon layer and injecting N+ ions; forming a gate insulation layer on the polysilicon layer; forming a second photoresist pattern on the gate insulation layer and injecting N? ions; forming a third photoresist pattern on the gate insulation layer and injecting P+ ions; forming a metal layer on the gate insulation layer so as to form a gate terminal; forming a hydrogenated insulation layer on the metal layer; forming a first ditch in the first insulation layer; and forming a second metal layer on the first insulation layer.

Abstract: An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.

Abstract: A gate electrode, an element isolation film and a drain region in an LDMOS transistor formation region and a gate electrode, an element isolation film and an anode region in an ESD protection element formation region are formed to satisfy relationships of A1?A2 and B1<B2 where the LDMOS transistor formation region has an overlap length A1 of the gate electrode and the element isolation film and a distance B1 between the gate electrode and the drain region, and the ESD protection element formation region has an overlap length A2 of the gate electrode and the element isolation film and a distance B2 between the gate electrode and the anode region.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract: Disclosed herein is a field effect transistor (FET), device including a FET, and a method of making the same. In embodiments of the disclosure, a semiconductor-on-insulator (SOI) substrate is provided. The SOI substrate includes a body having a first conductivity type formed in the semiconductor layer of the SOI substrate, the body including a first body region connecting a second body region to a third body region; and a source and a drain, each having a second conductivity type, disposed on opposite sides of the first body region. A first gate electrode having a second work function is disposed above the first body region; and a second gate electrode having a first work function disposed above the second and third body regions. A first gate dielectric layer may be disposed vertically between the first body region and the first gate electrode, and a second gate dielectric layer may be disposed vertically between the second and third body regions and the second gate electrode.

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.

Abstract: A microelectronic device and a method of forming same. The method comprises: a transistor gate; a first spacer and a second spacer respectively adjacent a first side and a second side of the gate; a diffusion layer supra-adjacent the gate; contact regions super-adjacent the diffusion layer and adjacent the first spacer and the second spacer; a protective cap super-adjacent the gate and between the contact regions, the protective cap being adapted to protect the device from shorts between the gate and the contact regions.

Abstract: A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die. Moreover, on the outer side of each edge cell, the second drain layer includes a region of reduced dopant density that extends beyond the gate electrode right to the adjacent edge of the die.

Abstract: An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region.

Abstract: An embodiment of an embedded cache memory in an image sensor comprises a memory cell array wherein the memory cells are substantially isolated from laterally adjacent memory. The memory cell array includes a plurality of memory cells. Each of the memory cells is formed in a standard CMOS image sensor process without the need for SOI processes. Each cell includes first and second n-type and p-type regions arranged around a vertically integrated gate. Data is written to a cell by causing carriers to accumulate in the body of the device through carrier generation mechanisms that may include impact ionization, band-to-band tunneling and/or channel-initiated secondary hot electrons.

Abstract: An insulated gate type thyristor includes: a first current terminal semiconductor region of a first conductivity type having a high impurity concentration; a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a low impurity concentration and formed on the first current terminal semiconductor region; a second base semiconductor region of the first conductivity type having a low impurity concentration and formed on the first base semiconductor region; a second current terminal semiconductor region of the second conductivity type having a high impurity concentration and formed on the second base semiconductor region; a trench passing through the second current terminal semiconductor region and entering the second base semiconductor region leaving some depth thereof, along a direction from a surface of the second current terminal semiconductor region toward the first base semiconductor region; and an insulated gate electrode structure formed in the trench.

Abstract: A dielectric material layer is formed over a workpiece, a metal layer is formed over the dielectric material layer, and a semiconductive material layer is formed over the metal layer. The workpiece is heated, causing a top portion of the metal layer to interact with the semiconductive material layer and causing a bottom portion of the metal layer to diffuse into the dielectric material layer. The metal layer portion that interacts with the semiconductive material layer forms a silicide, and the diffused metal layer portion forms a high dielectric constant gate material having a graded concentration of the metal from the metal layer. At least the semiconductive material layer and the dielectric material layer are patterned to form a gate and a gate dielectric of a transistor device. A source region and a drain region are formed in the workpiece proximate the gate and gate dielectric.

Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.