Abstract: The invention relates to a thin film transistor substrate for use in a liquid crystal display device and a method of fabricating the same, and an object is to provide a thin film transistor substrate which can ensure high reliability even though a low resistance metal is used in a material for a gate electrode and a predetermined wiring and a method of fabricating the same. A TFT substrate has a gate electrode in a multilayer structure configured of an AlN film as a nitrogen containing layer, an Al film as a main wiring layer and an upper wiring layer formed of an MoN film and an Mo film. On the gate electrode whose side surface inclines gently, a gate insulating film of excellent film quality is formed.

Abstract: Nonvolatile integrated circuit memory devices having a 2-bit memory cell include a substrate, a source region and a drain region in the substrate, a step recess channel between the source region and the drain region, a trapping structure including a plurality of charge trapping nano-crystals on the step recess channel, and a gate on the trapping structure. Related fabrication methods are also described.

Abstract: An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region.

Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.

Abstract: The present invention relates to a method of forming a metal feature on an intermediate structure of a semiconductor device that comprises a first exposed metal structure and a second exposed metal structure. The metal feature is selectively formed on the first exposed metal structure without forming on the second exposed metal structure. By adjusting a concentration of stabilizer in an electroless plating solution, the metal feature is electrolessly plated on the first exposed metal structure without plating metal on the second exposed metal structure.

Abstract: A semiconductor high-voltage device including a semiconductor substrate having a deep trench formed therein, a gate oxide film formed on sidewalls of the deep trench, a polysilicon layer formed in the deep trench and on the gate oxide film, and spacers formed on sidewalls of the trench at a portion of the deep trench above the gate oxide film. Loss of a gate oxide film can be prevented during processing, thereby also preventing a change of a current path, a phenomenon such as current leakage between a top surface of polysilicon and source/drain regions.

Abstract: A transistor having an electrode layer that can reduce or prevent a coupling effect, a fabricating method thereof, and an image sensor having the same are provided. The transistor includes a semiconductor substrate and a well of a first conductivity type formed on the semiconductor substrate. A heavily-doped first impurity region of a first conductivity type surrounds an active region defined in the well. Heavily-doped second and third impurity regions of a second conductivity type are spaced apart from each other in the active region an define a channel region interposed therebetween. A gate is formed over the channel region to cross the active region. The gate overlaps at least a portion of the first impurity region and receives a first voltage. An electrode layer is formed between the semiconductor substrate and the gate, such that the electrode layer overlaps a portion of the first impurity region contacting the channel region and receives a second voltage.

Abstract: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain is obtained through non symmetric placement of stress inducing structures as part of the gate electrode. Silicon nitride layers may be placed on one side of the gate electrode in a compressive mode, or on the other side of the gate electrode in a tensile mode to obtain similar results.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: A primitive cell having a gate pattern that is robust against ESD is provided. The primitive cell comprises: a high finger PMOS transistor and a low finger NMOS transistor. The high finger PMOS transistor has a first terminal connected to a high power source, and a gate to which a control voltage is applied and which has a plurality of fingers. The low finger NMOS transistor has a first terminal connected to a low power source, a gate to which the control voltage is applied and which has a plurality of fingers, and a second terminal connected to a second terminal of the PMOS transistor. The number of the fingers of the gate of the NMOS transistor is smaller than the number of fingers of the gate of the PMOS transistor and the length of each of the fingers of the NMOS transistor is greater than the length of each of the fingers of the PMOS transistor.

Abstract: A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.

Abstract: A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.

Abstract: A semiconductor device has a substrate, a first gate electrode, and a second gate electrode. The substrate has an active region surrounded by an isolation region. The first gate electrode is formed on the active region through a gate insulating film. The second gate electrode is formed on the gate insulating film such that the second gate electrode overlaps at least a part of a boundary between the active region and the isolation region. The first gate electrode and the second gate electrode are separated from each other.

Abstract: The semiconductor device 1 includes transistors 10, 20. Each of the transistors 10 (first transistor) is a MOSFET, and includes source regions 102, 106, a drain region 104, and a gate electrode 110. Each of the transistors 20 (second transistor) is also a MOSFET, and includes source regions 202, 206, a drain region 204, and a gate electrode 210. The source region 106 of the transistor 10 and the source region 202 of the transistor 20 are the identical region in the semiconductor substrate 90. In other words, the source region 106 and the source region 202 are shared by the both transistors.

Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.

Abstract: Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.

Abstract: A semiconductor device includes a base region formed above a semiconductor substrate, a source region formed above the base region, a gate electrode filled inside a trench formed above the semiconductor substrate, an interlayer insulation film formed all over the semiconductor substrate, a first contact hole formed in the interlayer insulation film to expose the gate electrode, a second contact hole formed in the interlayer insulation film and the source region to expose the base region, and a conductive film formed above a trench where the first contact hole is formed.

Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

Abstract: A semiconductor high-voltage device including a semiconductor substrate having a deep trench formed therein, a gate oxide film formed on sidewalls of the deep trench, a polysilicon layer formed in the deep trench and on the gate oxide film, and spacers formed on sidewalls of the trench at a portion of the deep trench above the gate oxide film. Loss of a gate oxide film can be prevented during processing, thereby also preventing a change of a current path, a phenomenon such as current leakage between a top surface of polysilicon and source/drain regions.

Abstract: A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by reacting a metal and the regrown polycrystalline region having the increased grain size.

Abstract: According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to extend over a main surface of the semiconductor substrate. Source/drain regions having a first conductivity are disposed in the active region at both sides of the channel trench. A channel impurity region having a second conductivity is disposed beneath one of the source/drain regions to be in contact with at least a sidewall of the channel trench.

Abstract: A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.

Abstract: Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

Abstract: A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.

Abstract: The invention relates to a manufacturing method for an insulated gate semiconductor device cell, comprising the steps of forming a cell window (3) in a layered structure that is located on top of a semiconductor substrate (1), forming at least one process mask that partially covers the cell window (3). In forming the cell window (3), at least one strip (41, 42) of the layered structure is left to remain inside the cell window (3) and at least one strip (41, 42) is used to serve as an edge for the at least one process mask (51, 52). The invention further relates to an insulated gate semiconductor device, comprising a semiconductor substrate (1) having an essentially planar top surface and an insulated gate formed on the top surface by a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41, 42) of the layered structure (2) is disposed on a third area of the top surface between an edge of the insulated gate and a first main contact (6).

Abstract: Provided is a non-planar transistor with a multi-gate structure that includes a germanium channel region, and a method of manufacturing the same. The non-planar transistor includes a silicon body and a channel region that covers exposed surfaces of the silicon body. The channel region is formed of a germanium layer and includes a first channel region and a second channel region. In order to form the germanium channel region, a mesa type active region is formed on the substrate, and a germanium layer is formed to cover two sidewalls and an upper surface of the active region.

Abstract: A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.

Abstract: A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide.