Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract: A method of fabricating a liquid crystal display device according to an embodiment of the present invention includes forming first and second conductive layers on a substrate, wherein the first layer is transparent; patterning the second conductive layer and the first conductive layer using the photo-resist pattern as a mask; etching at least one lateral part of the patterned second conductive layer using the photo-resist pattern as a mask; and removing the remaining photo-resist pattern.

Abstract: A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate insulating layer formed overlying the active layer has a central region, a shielding region and an extending region. The shielding region is disposed between the central region and the extending region, the central region covers the channel region, the shielding region covers the first doped region, and the extending region covers the second doped region. The shielding region is thicker than the extending region. A gate layer is formed overlying the gate insulating layer, covers the central region and exposes the shielding region and the extending region.

Abstract: A semiconductor device may include at least one pair of fins on a semiconductor substrate. A channel region may be formed in each fin. The semiconductor device may further include a gate electrode corresponding to each pair of channel regions, a source contact plug electrically connected to each of at least one source formed on a respective fin concurrently, and a drain contact plug electrically connected to each of at least one drain formed on a respective fin concurrently.

Abstract: A method of manufacturing a thin-film semiconductor device substrate includes a step of forming a non-single crystalline semiconductor thin film on a base layer, and an annealing step of irradiating the non-single crystalline semiconductor thin film with an energy beam to enhance crystallinity of a non-single crystalline semiconductor constituting the non-single crystalline semiconductor thin film. The annealing step includes simultaneously irradiating the non-single crystalline semiconductor thin film with a plurality of energy beams to form a plurality of unit regions each including at least one irradiated region irradiated with the energy beam and at least one non-irradiated region that is not irradiated with the energy beam.

Abstract: A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall of a first block of material. The method further comprises scanning a first primary ion beam impinging on the first target surface with an incident angle ? different from zero degrees and thereby inducing a first secondary ion beam, and doping at least the left sidewall surface and possibly the top surface of the fin opposite to the first target surface with the first secondary ion beam.

Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.

Abstract: A polysilicon thin film transistor device includes a gate metal pattern including a gate electrode and a gate line formed on a substrate, the gate metal pattern having a stepped portion, a gate insulating film formed on the gate metal pattern, a polysilicon semiconductor layer formed on the gate insulating film, the polysilicon semiconductor layer including an active region, lightly doped drain regions, a source region, and a drain region, a source electrode connected to the source region and a drain electrode connected to the drain region on the polysilicon semiconductor layer, and a pixel electrode connected with the drain electrode.

Abstract: A TFT device, a method of manufacturing the same, a TFT substrate and a display device, making it possible to decrease the photolithography steps, to improve the productivity and to decrease the cost of production. There are formed on the same substrate a first n-ch TFT having an LDD region which is entirely covered with a gate electrode, a second n-ch TFT having an LDD region partially covered with a gate electrode, and a p-ch TFT. Here, electrically conducting thin films and a gate electrode are formed on the electrically conducting thin film and on the insulating film, phosphorus ions are implanted into source/drain regions of the n-ch TFTs using the electrically conducting thin films and gate electrode as masks, and a gate electrode is formed by etching the electrically conducting thin film by using the electrically conducting thin film as a mask.

Abstract: There is provided a semiconductor device having TFTs whose thresholds can be controlled. There is provided a semiconductor device including a plurality of TFTs having a back gate electrode, a first gate insulation film, a semiconductor active layer a second gate insulation film and a gate electrode, which are formed on a substrate, wherein an arbitrary voltage is applied to the back gate electrode.

Abstract: A thin film transistor and a pixel structure with the same are disclosed. The thin film transistor includes a gate electrode with at least one notch, a gate dielectric layer, a source region, a drain region, and a channel layer. The gate electrode is on a substrate. The gate dielectric layer is on the substrate and covers the gate electrode. The source region is on the gate dielectric layer, wherein it is over a region outside the notch of the gate electrode and overlaps a portion of the gate electrode. The drain region is on the gate dielectric layer, wherein it is over the notch of the gate electrode and overlaps the gate electrode at the edge of the notch. Further, the channel layer is on the gate dielectric layer and between the source and drain regions. Due to asymmetric design of the source and drain regions, the parasitic capacitance change can be substantially reduced when a misalignment of the upper and lower metal layers occurs.

Abstract: The invention relates to a manufacturing method for an insulated gate semiconductor device cell, comprising the steps of forming a cell window (3) in a layered structure that is located on top of a semiconductor substrate (1), forming at least one process mask that partially covers the cell window (3). In forming the cell window (3), at least one strip (41, 42) of the layered structure is left to remain inside the cell window (3) and at least one strip (41, 42) is used to serve as an edge for the at least one process mask (51, 52). The invention further relates to an insulated gate semiconductor device, comprising a semiconductor substrate (1) having an essentially planar top surface and an insulated gate formed on the top surface by a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41, 42) of the layered structure (2) is disposed on a third area of the top surface between an edge of the insulated gate and a first main contact (6).

Abstract: A thin film transistor formed by using a Metal Induced Lateral Crystallization process and method for fabricating the same. The thin film transistor comprises an active layer having source/drain regions and a channel region, a gate electrode, an insulating layer having contact holes for exposing a portion of each of the source/drain regions, and a crystallization inducing pattern exposing a portion of the active layer. The source/drain electrodes are coupled to the source/drain regions through the contact holes, and the crystallization inducing pattern does not couple the source/drain regions to the source/drain electrodes.

Abstract: Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.

Abstract: A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

Abstract: To satisfy the different requirement of TFTs function as peripheral driving circuit and pixel switching device, the modified TFT structure with various thicknesses of gate insulating layers is disclosed. For the peripheral driving circuit, the thinner thickness of the gate-insulating layer is formed, the higher driving ability the TFT performs. However, for the pixel switching device, the thicker thickness of the gate insulating layer is formed, the better reliability the TFT has. The present invention provides a first TFT (peripheral driving circuit) comprising a first gate insulating layer and a second TFT (pixel switching device) comprising a first and second gate insulating layer. Thus, the gate insulating layer of the peripheral driving circuit has a thickness less then that of the pixel switching device.

Abstract: A semiconductor device that uses a high reliability TFT structure is provided. The gate electrode of an n-channel type TFT is formed by a first gate electrode and a second gate electrode that covers the first gate electrode. LDD regions have portions that overlap the second gate electrode through a gate insulating film, and portions that do not overlap. As a result, the TFT can be prevented from degradation in an ON state, and it is possible to reduce the leak current in an OFF state.

Abstract: Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET region and removing the SiGe film exposing the top surface of the Si film in an NFET region. Anneal to drive Ge into the Si film in the PFET region. Deposit a gate electrode layer covering the SiGe film in the PFET region and cover the exposed portion of the Si film in the NFET region. Pattern and etch the gate electrode layer to form gates. Form FET devices with sidewall spacers and source regions and drains regions in the substrate aligned with the gates.

Abstract: A method of manufacturing a thin-film semiconductor device substrate includes a step of forming a non-single crystalline semiconductor thin film on a base layer, and an annealing step of irradiating the non-single crystalline semiconductor thin film with an energy beam to enhance crystallinity of a non-single crystalline semiconductor constituting the non-single crystalline semiconductor thin film. The annealing step includes simultaneously irradiating the non-single crystalline semiconductor thin film with a plurality of energy beams to form a plurality of unit regions each including at least one irradiated region irradiated with the energy beam and at least one non-irradiated region that is not irradiated with the energy beam.