Abstract: The present invention relates a method for forming a monocrystalline GeN layer (4) on a substrate (1) comprising at least a Ge surface (3). The method comprises, while heating the substrate (1) to a temperature between 550° C. and 940° C., exposing the substrate (1) to a nitrogen gas flow. The present invention furthermore provides a structure comprising a monocrystalline GeN layer (4) on a substrate (1). The monocrystalline GeN formed by the method according to embodiments of the invention allows passivation of surface states present at the Ge surface (3).

Abstract: A semiconductor device has a semiconductor layer, and a first electrode (Schottky electrode or MIS electrode) and a second electrode (ohmic electrode) which are formed on the semiconductor layer apart from each other. The first electrode has a cross section in the shape of a polygon. A second electrode-side corner of the polygon has an interior angle of which an outward extension line of a bisector crosses the semiconductor layer or the second electrode. The interior angle of such a second electrode-side corner is larger than 90°.

Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.

Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode.

Abstract: A semiconductor device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, a contact trench extending through the source and at least part of the body, a contact electrode disposed in the contact trench, and an epitaxial enhancement portion disposed below the contact trench, wherein the epitaxial enhancement portion has the same carrier type as the epitaxial layer.

Abstract: A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n? GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n?, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal, and an ohmic contact is deposited on the n+ layer.

Abstract: A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises ?-tungsten.

Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.

Abstract: A merged PN/Schottky diode is provided having a substrate of a first conductivity type and a grid of doped wells of the second conductivity type embedded in the substrate. A Schottky barrier metal layer makes a Schottky barrier contact with the surface of the substrate above the grid. Selected embedded wells in the grid make a Schottky barrier contact to the Schottky barrier metal layer, while most embedded wells do not. The diode forward voltage drop is reduced for the same diode area with reverse blocking benefits similar to a conventional JBS structure.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a localized region of doping near a portion of a channel region where current exits during operation.

Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.

Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.

Abstract: A Schottky diode includes at least a trenched opened in a semiconductor substrate doped with a dopant of a first conductivity type wherein the trench is filled with a Schottky junction barrier metal. The Schottky diode further includes one or more dopant region of a second conductivity type surrounding sidewalls of the trench distributed along the depth of the trench for shielding a reverse leakage current through the sidewalls of the trench. The Schottky diode further includes a bottom-doped region of the second conductivity type surrounding a bottom surface of the trench and a top-doped region of the second conductivity type surrounding a top portion of the sidewalls of the trench. In a preferred embodiment, the first conductivity type is a N-type conductivity type and the middle-depth dopant region comprising a P-dopant region.

Abstract: To provide a Schottky electrode in a diamond semiconductor, which has a good adhesion properties to diamonds, has a contacting surface which does not become peeled due to an irregularity in an external mechanical pressure, does not cause a reduction in yield in a diode forming process and does not cause deterioration in current-voltage characteristics, and a method of manufacturing the Schottky electrode. A Schottky electrode which includes: scattered island-form pattern Pt-group alloy thin films which are formed on a diamond surface formed on a substrate, in which the Pt-group alloy includes 50 to 99.9 mass % of Pt and 0.

Abstract: An integrated circuit structure is described, and includes a substrate, a contact window, and a Schottky contact metal layer. A heavily doped region and a lightly doped region are formed in the substrate. The contact window is disposed above the heavily doped region, and the Schottky contact metal layer is disposed above the lightly doped region. The Schottky contact metal layer and the substrate form a Schottky diode. The material of the contact window is different from that of the Schottky contact metal layer.

Abstract: An ultrafast recovery diode. In a first embodiment, a rectifier device comprises a substrate of a first polarity, a lightly doped layer of the first polarity coupled to the substrate and a metallization layer disposed with the lightly doped layer. The ultrafast recovery diode includes a plurality of wells, separated from one another, formed in the lightly doped layer, comprising doping of a second polarity. The plurality of wells connect to the metallization layer. The ultrafast recovery diode further includes a plurality of regions, located between wells of said plurality of wells, more highly doped of the first polarity than the lightly doped layer.

Abstract: A trench Schottky barrier rectifier includes an cathode electrode at a face of a semiconductor substrate and an multiple epitaxial structure in drift region which in combination provide high blocking voltage capability with low reverse-biased leakage current and low forward voltage. The multiple structure of the drift region contains a concentration of first conductivity dopants therein which comprises two or three different uniform value from a Schottky rectifying junction formed between the anode electrode and the drift region. The thickness of the insulating region (e.g., SiO2) in the MOS-filled trenches is greater than 1000 ? to simultaneously inhibit field crowing and increase the breakdown voltage of the device. The multiple epi structure is preferably formed by epitaxial growth from the cathode region and doped in-situ.

Abstract: A semiconductor diode that eliminates leakage current and reduces parasitic resistance is disclosed. The semiconductor diode comprises a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate, wherein the semiconductor layer includes a first dopant and a first well with a Schottky region; and a polysilicon device positioned above the semiconductor layer and adjacent to the first well with the Schottky region.

Abstract: A nonvolatile semiconductor memory device comprises: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends, a transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than a first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage; a load circuit connected to the variable resistive element in series having an adjustable load resistance; and a voltage generation circuit for applying a voltage to both ends of a serial circuit; wherein the variable resistive element can transit between the states by adjusting a resistance of the load circuit.

Abstract: A semiconductor device which is suitable for miniaturization, capable of improving variations in characteristics of a transistor and enhancing the current driving capability comprises a semiconductor substrate, an isolation protruding from the semiconductor substrate and having a width above the semiconductor substrate narrower than a width in the semiconductor substrate, a semiconductor layer formed on the semiconductor substrate portion between the isolations, and a MOSFET formed on the semiconductor layer.

Abstract: The present invention relates to semiconductor electronic devices including molybdenum oxide formed on substrates which consist of materials which are used in known semiconductor electronic devices. The present invention relates to also a new method to fabricate said electronic devices on substrates made of materials which have been used in usual electronic and photonic devices. Suitable substrates consist of materials such as element semiconductors such as silicon and germanium, III-V compound semiconductors such as gallium arsenide and gallium phosphide, II-IV compound semiconductors such as zinc oxide, IV compound semiconductors, organic semiconductors, metal crystals and their derivatives or glasses.

Abstract: A method includes forming a first conductive type buried layer on a semiconductor substrate, forming a second conductive type epi-layer on the semiconductor substrate using an epitaxial growth method such that the epi-layer surrounds the buried layer, forming a first conductive type plug from the surface of the semiconductor substrate to the buried layer, forming a first conductive type well, which is horizontally spaced from the first conductive type plug, from the surface of the semiconductor substrate to the buried layer, and forming a plurality of metal contacts as an anode and cathode of the schottky diode, respectively, by making electrical connection to the well and plug.

Abstract: A semiconductor device that includes an n-type semiconductor substrate and an upper electrode formed on an upper face of the semiconductor substrate and a method of manufacturing the semiconductor device are provided. A p-type semiconductor region is repeatedly formed in the semiconductor substrate in at least one direction parallel to the substrate plane so as to be exposed on an upper face of the semiconductor substrate. The upper electrode includes a metal electrode portion; and a semiconductor electrode portion made of a semiconductor material whose band gap is narrower than that of the semiconductor substrate. The semiconductor electrode portion is provided on each p-type semiconductor region exposed on the upper face of the semiconductor substrate. The metal electrode portion is in Schottky contact with an n-type semiconductor region exposed on the upper face of the semiconductor substrate, and is in ohmic contact with the semiconductor electrode portion.

Abstract: A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region, and has a fixed-charge containing region which contains a fixed charge and extends across a boundary between the semiconductor and the electrically conductive region.

Abstract: A semiconductor device has a first region and a second region formed on a surface of a substrate. Plural first conductors and second conductors are formed in the first and second regions respectively. A first semiconductor region and a second semiconductor region are formed between adjacent first conductors. The second semiconductor region is in the first semiconductor region and has a conductivity type opposite to that of the first semiconductor. A third semiconductor region is formed between adjacent second conductors. The third semiconductor region has the same conductivity type as the second semiconductor region and is lower in density than the second semiconductor region. The third semiconductor region has a metal contact region for contact with a metal, which is electrically connected to the second semiconductor region. A center-to-center distance between adjacent first conductors is smaller than that between adjacent second conductors.

Abstract: A semiconductor structure comprises a semiconductor substrate. A layer of an electrically insulating material is formed over the semiconductor substrate. An electrically conductive feature is formed in the layer of electrically insulating material. A first layer of a semiconductor material is formed between the electrically conductive feature and the layer of electrically insulating material.

Abstract: An apparatus to store electrical energy is provided. The apparatus includes a first magnetic section, a second magnetic section, and a semiconductor section configured between the first magnetic section and the second magnetic section, wherein the junction between the semiconductor section and the first and second magnetic section forms a diode barrier preventing current flow to store electrical energy.

Abstract: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 ?-?m2 or even less than or equal to 1 ?-?m2 for the electrical device.

Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.

Abstract: In one embodiment, a semiconductor structure comprises a multi-portioned guard ring that includes a first portion and a second portion formed in a region of semiconductor material. A conductive contact layer forms a first Schottky barrier with the region of semiconductor material. The conductive contact layer overlaps the second portion and forms a second Schottky barrier that has an opposite polarity to the first Schottky barrier. The conductive contact layer does not overlap the first portion, which forms a pn junction with the region of semiconductor material.

Abstract: To provide a nonvolatile memory which realizes nonvolatile characteristic similar to a flash memory and a high-speed access equivalent to SRAM, has an integration degree exceeding that of DRAM, requires low voltage and low power consumption, and can be driven by a small-size battery, there are provided: (1) a non-volatile memory, including: a pair of metal electrodes; and a nano-hole-containing metal oxide film having a film thickness of 0.

Abstract: A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide is formed between the body contact and the SOI layer as a result of the reaction of the barrier metal and the SOI layer.

Abstract: A charge coupled device (CCD) is disclosed which has a semiconductor body (20) comprising polymer or oligomer semiconductor material in place of the conventional silicon. A back electrode (22) of the device is electrically coupled to the semi-conductor body through a Schottky junction, reducing the availability of holes in the semiconductor body. Shift electrodes forming a shift register are driven by negative electrical potentials and accumulations of holes in p type semiconductor material represent data.

Abstract: A method of forming a rectifying diode. The method comprises providing a first semiconductor region of a first conductivity type and having a first dopant concentration and forming a second semiconductor region in the first semiconductor region. The second semiconductor region has the first conductivity type and having a second dopant concentration greater than the first dopant concentration. The method also comprises forming a conductive contact to the first semiconductor region and forming a conductive contact to the second semiconductor region. The rectifying diode comprises a current path, and the path comprises: (i) the conductive contact to the first semiconductor region; (ii) the first semiconductor region; (iii) the second semiconductor region; and (iv) the conductive contact to the second semiconductor region. The second semiconductor region does not extend to a layer buried relative to the first semiconductor region.

Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.

Abstract: The present invention provides a Schottky barrier semiconductor device having a semiconductor substrate 101, a low-concentration semiconductor layer 102, trenches 103 formed in the low-concentration semiconductor layer 102 and extending to the semiconductor substrate 101, and a mesa portion 102a formed between the trenches 103. This provides a high durability against a surge or transient voltage.

Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may, be formed under a portion of the schottky junction.

Abstract: A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (?) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.

Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.

Abstract: A field effect transistor includes a semiconductor substrate having an active region, a source region, and a drain region at an upper portion of the substrate. The active region is located between the source and drain regions. A gate electrode is located on the active region. A source electrode is located on the source region and forms an ohmic contact with the source region. A drain electrode has a base part on and in ohmic contact with the drain region and an extended part having edge close to the gate electrode and over a boundary between the active region and the drain region. An insulating film is located between the boundary and the extended part and has a thickness that increases along a direction from the drain electrode toward the gate electrode in a step-by-step or continuous manner.

Abstract: A semiconductor device is disclosed. The device has a first and second electrode formed in a semiconductor substrate. The first and second electrode are separated from each other by a semiconductor region. and the device also includes a third electrode for controlling conductivity of the semiconductor region. At least one of the first and second electrodes forms a rectifying contact with the semiconductor region. The rectifying contact has a potential barrier. The semiconductor region is uniformly doped, at least in a direction between the first and the second electrodes, to have a doping level higher than the doping level of the semiconductor substrate and so as to, in operation, induce an image-force mechanism for lowering the potential barrier of the at least one rectifying contact.

Abstract: A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second doped region is disposed between the first doped region and the first conductive layer. The plurality of third doped regions are disposed in the second doped region. The first doped region of the semiconductor is heavily doped with a first type of dopant (e.g., phosphorous or arsenic). The second doped region is moderately doped with the first type of dopant. The plurality of third doped regions are moderately to heavily doped with a second type of dopant.

Abstract: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a). If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source (3a) and the (ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannot be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.