Abstract: A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

Abstract: Apparatus and methods are disclosed, such as those involving protection of a semiconductor junction of a semiconductor device. One such apparatus includes a bipolar transistor including an emitter, a base, and a collector; a first junction protection device including a first end electrically coupled to the emitter of the bipolar transistor, and a second end electrically coupled to a node; and a second junction protection device including a first end electrically coupled to a voltage reference, and a second electrically coupled to the emitter of the bipolar transistor. Each of the first and second junction protection devices may have a substantially higher leakage current than the leakage current of the base-emitter junction of the bipolar transistor when reverse biased.

Abstract: A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than 100 ?. A first Schottky barrier junction is formed at the interface of the first semiconductor barrier region and the one or more conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.

Abstract: A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.

Abstract: A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).

Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

Abstract: A method of forming a Schottky barrier contact to a semiconductor material, includes the following steps: depositing an iridium contact on a surface of the semiconductor material; and annealing the iridium contact to form a Schottky barrier contact to the semiconductor material. For an example of an iridium Schottky contact on an InAlAs semiconductor material, the annealing temperature is preferably in the range about 350° C. to 500° C.

Abstract: A Schottky barrier MOSFET (SB-MOS) device and a method of manufacturing having a silicon-on-nothing (SON) architecture in a channel region is provided. More specifically, metal source/drain SB-MOS devices are provided in combination with a channel structure comprising a semiconductor channel region such as silicon isolated from a bulk substrate by an SON dielectric layer. In one embodiment, the SON dielectric layer has a triple stack structure comprising oxide on nitride on oxide, which is in contact with the underlying semiconductor substrate.