Abstract: Systems and methods are disclosed and described for correcting errors in ASR transcriptions. For an incorrect transcription, different words or phrases from the transcription, and/or related words or phrases, are submitted as hint words to the ASR system, and the voice query is submitted again, to determine new transcriptions. This process is repeated with different transcription terms, until a different and more proper transcription is generated. This increases the accuracy of ASR systems.

Abstract: An integrated circuit includes a transistor having a collector region, a base region and an emitter strip. The collector region includes layer of a semiconductor substrate doped with a dopant of a first conductivity type. The base region includes semiconductor layer over the semiconductor substrate, doped with a dopant of a second conductivity type. An emitter strip within the base region has a first width and is doped with a first dopant of the first conductivity type. A plurality of emitter contacts is located within the emitter strip. Each emitter contact has a second width less than the first width, and includes a second dopant of the first conductivity type. Each emitter contact is spaced from a nearest neighbor emitter contact by a portion of the emitter strip. In some examples the transistor has a common-emitter current gain greater than 3500.

Abstract: Multiple bipolar transistors are disposed side by side in the first direction on a substrate. Multiple first capacitance devices are provided corresponding to the respective base electrodes of the bipolar transistors. A radio frequency signal is supplied to the bipolar transistors through the first capacitance devices. Resistive devices are provided corresponding to the respective base electrodes of the bipolar transistors. A base bias is supplied to the bipolar transistors through the resistive devices. The first capacitance devices are disposed on the same side relative to the second direction orthogonal to the first direction, when viewed from the bipolar transistors. At least one of the first capacitance devices is disposed so as to overlap another first capacitance device partially when viewed in the second direction from the bipolar transistors.

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor on a semiconductor fin and methods to form the same. A bipolar transistor structure according to the disclosure may include a doped semiconductor layer coupled to a base contact. A first semiconductor fin on the doped semiconductor layer may have a first doping type. An emitter/collector (E/C) material may be on a sidewall of an upper portion of the first semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.

Abstract: A device includes a buried oxide layer disposed on a substrate, a first region disposed on the buried oxide layer and a first ring region disposed in the first region. The first ring region includes a portion of a guardring. The device further includes a first terminal region disposed in the first ring region, a second ring region disposed in the first region and a second terminal region disposed in the second ring region. The first terminal region is connected to an anode and the second terminal region is connected to a cathode. The first region has a graded doping concentration. The first region, the second ring region and the second terminal region have a first conductivity type, and the first ring region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.

Abstract: A semiconductor die includes a transistor with an emitter, base, and collector. The base includes an intrinsic base that is located in monocrystalline semiconductor material grown in an opening of a first semiconductor layer. A second semiconductor layer is located above the first semiconductor layer and includes a monocrystalline portion. In some embodiments, an opening was formed in the second semiconductor layer wherein a portion of the underlying first semiconductor layer was etched to form a cavity in which a monocrystalline intrinsic base was grown.

Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.

Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: A semiconductor device includes a bipolar junction transistor having a collector, a base, and an emitter. The collector includes a current collection region, a constriction region laterally adjacent to the current collection region, and a contact region laterally adjacent to the constriction region, located opposite from the current collection region. The current collection region, the constriction region laterally, and the contact region all have the same conductivity type. The base includes a current transmission region contacting the current collection region and a constricting well laterally adjacent to, and contacting, the current transmission region and contacting the constriction region. The current transmission region and the constricting well have an opposite conductivity type than the current collection region, the constriction region laterally, and the contact region.

Abstract: Aspects of the disclosure provide a bipolar transistor structure with an elevated extrinsic base, and related methods to form the same. A bipolar transistor according to the disclosure may include a collector on a substrate, and a base film on the collector. The base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region. An emitter is on a first portion of the crystalline region of the base film. An elevated extrinsic base is on a second portion of the crystalline region of the base film, and adjacent the emitter.

Abstract: Aspects generally relate to a heterojunction bipolar transistor (HBT), and method of manufacturing the same. The HBT including an emitter a first, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter. A collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter. A dielectric coupled to the collector. A first conductive base contact coupled to the base and adjacent to the collector and extending over a base-collector junction, the conductive base contact operative as a field plate.

Abstract: Systems and methods are disclosed and described for correcting errors in ASR transcriptions. For an incorrect transcription, different words or phrases from the transcription, and/or related words or phrases, are submitted as hint words to the ASR system, and the voice query is submitted again, to determine new transcriptions. This process is repeated with different transcription terms, until a different and more proper transcription is generated. This increases the accuracy of ASR systems.

Abstract: A semiconductor device, its manufacturing method, and a radiation measurement method are presented, relating to semiconductor techniques. The semiconductor device includes: a substrate comprising a base area and a collector area adjacent to each other; a plurality of semiconductor fins on the substrate, wherein the plurality of semiconductor fins comprises at least a first semiconductor fin and a second semiconductor fin on the base area and separated from each other, the first semiconductor fin comprises an emission area adjacent to the base area, and the second semiconductor fin comprises a first region adjacent to the base area; a first gate structure on the second semiconductor fin; and a first source and a first drain at two opposite sides of the first gate structure and at least partially in the first region. Radiation in a semiconductor apparatus can be measured through this semiconductor device.

Abstract: A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a second control gate, a first output node against which the first moveable beam can be positioned. The data storage cell also comprises a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and a fourth control gate. The second moveable beam can be positioned against the first output node. Further, the first nano electromechanical switch and the second nano electromechanical switch are configured for selecting a first or a second state of the data storage cell and are configured for having their moveable beam complementary positioned to the first output node.

Abstract: The presence or absence of touch is detected according to a difference of a capacitance caused by the presence or absence of a material that blocks the electric field formed between the detection electrode and the common electrode. The common electrode includes a plurality of divided electrode portions that is extended in a lateral direction and aligned with each other in a longitudinal direction. Each of the plurality of common lines is electrically connected to at least one of the divided electrode portions. The plurality of common lines is arranged in an area next to the common electrode in the lateral direction of the common electrode, arranged next to each other in a width direction orthogonal to a length thereof, is different in width from each other, and the width of the common lines is wider as the length is longer.

Abstract: A semiconductor device including a protection device and a protected device, the protection device includes a first semiconductor region of a second conductivity type formed over a substrate, a second semiconductor region of the second conductivity type provided in the first semiconductor region, having a higher impurity concentration than the first semiconductor region, a third semiconductor region of the second conductivity type formed in a surface layer of the second semiconductor region, having a higher impurity concentration than the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in the first semiconductor region and located away from the third semiconductor region, having a higher impurity concentration than the first semiconductor region, a fifth semiconductor region of a first conductivity type formed in the first semiconductor region and electrically short-circuited with the fourth semiconductor region, and a sixth semiconductor region of the first c

Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.

Abstract: Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base.

Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.

Abstract: Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.

Abstract: According to one exemplary embodiment, a fin-based bipolar junction transistor (BJT) includes a wide collector situated in a semiconductor substrate. A fin base is disposed over the wide collector. Further, a fin emitter and an epi emitter are disposed over the fin base. A narrow base-emitter junction of the fin-based BJT is formed by the fin base and the fin emitter and the epi emitter provides increased current conduction and reduced resistance for the fin-based BJT. The epi emitter can be epitaxially formed on the fin emitter and can comprise polysilicon. Furthermore, the fin base and the fin emitter can each comprise single crystal silicon.

Abstract: A bipolar transistor having an upper surface, comprises a multilevel collector structure formed in a base region of opposite conductivity type and having a first part of a first vertical extent coupled to a collector contact, an adjacent second part having a second vertical extent a third part of a third vertical extent and desirably of a depth different from a depth of the second part, coupled to the second part by a fourth part desirably having a fourth vertical extent less than the third vertical extent. A first base region portion overlies the second part, a second base region portion separates the third part from an overlying base contact region, and other base region portions laterally surround and underlie the multilevel collector structure. An emitter proximate the upper surface is laterally spaced from the multilevel collector structure. This combination provides improved gain, Early Voltage and breakdown voltages.

Abstract: High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.

Abstract: An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.

Abstract: An electrostatic discharge (ESD) protection device includes a well region formed from semiconductor material with a first doping type and a floating base formed from semiconductor material with a second doping type. The floating base is disposed vertically above the well region. The ESD also includes a first terminal receiving region formed from semiconductor material with a third doping type. The first terminal receiving region is disposed vertically above the floating base. The ESD further includes a second terminal receiving region. The second terminal receiving region is laterally spaced apart from the first terminal receiving region by silicon trench isolation (STI) region. In some embodiments, the second terminal receiving region is formed from semiconductor material with the third doping type to form a bipolar junction transmitter (BJT) or with a fourth doping type to form a silicon controlled rectifier (SCR).

Abstract: A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.

Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates.

Abstract: Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes.

Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.

Abstract: According to various embodiments, a distributed heating transistor includes: a plurality of active regions where transistor action occurs including a heat source; and at least one inactive region where transistor action does not occur and no heat source is present, wherein adjacent active regions are separated by the at least one inactive region. The distributed heating transistor may be configured as field effect transistors (FETs), and bipolar junction transistors (BJTs). Methods for forming the distributed heating transistors are also provided.

Abstract: A method of fabricating a bipolar transistor including emitter and base regions having first and second conductivity types, respectively, includes forming an isolation region at a surface of a semiconductor substrate, the isolation region having an edge that defines a boundary of an active area of the emitter region, and implanting dopant of the second conductivity type through a mask opening to form the base region in the semiconductor substrate. The mask opening spans the edge of the isolation region such that an extent to which the dopant passes through the isolation region varies laterally to establish a variable depth contour of the base region.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.

Abstract: A bipolar transistor having an upper surface, comprises a multilevel collector structure formed in a base region of opposite conductivity type and having a first part of a first vertical extent coupled to a collector contact, an adjacent second part having a second vertical extent a third part of a third vertical extent and desirably of a depth different from a depth of the second part, coupled to the second part by a fourth part desirably having a fourth vertical extent less than the third vertical extent. A first base region portion overlies the second part, a second base region portion separates the third part from an overlying base contact region, and other base region portions laterally surround and underlie the multilevel collector structure. An emitter proximate the upper surface is laterally spaced from the multilevel collector structure. This combination provides improved gain, Early Voltage and breakdown voltages.

Abstract: An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail.

Abstract: An electrostatic discharge (ESD) protection clamp (21, 21?, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21?, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (?Vt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21?, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

Abstract: A higher breakdown voltage transistor has separated emitter, base contact, and collector contact. Underlying the emitter and the base contact are, respectively, first and second base portions of a first conductivity type. Underlying and coupled to the collector contact is a collector region of a second, opposite, conductivity type, having a central portion extending laterally toward, underneath, or beyond the base contact and separated therefrom by the second base portion. A floating collector region of the same conductivity type as the collector region underlies and is separated from the emitter by the first base portion. The collector and floating collector regions are separated by a part of the semiconductor (SC) region in which the base is formed. A further part of the SC region in which the base is formed, laterally bounds or encloses the collector region.

Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.

Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.

Abstract: Systems and methods are disclosed for processing radio frequency (RF) signals using one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.

Abstract: An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation.

Abstract: An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other.

Abstract: Diodes and bipolar junction transistors (BJTs) are formed in IC devices that include fin field-effect transistors (FinFETs) by utilizing various process steps in the FinFET formation process. The diode or BJT includes an isolated fin area and fin array area having n-wells having different depths and a p-well in a portion of the fin array area that surrounds the n-well in the isolated fin area. The n-wells and p-well for the diodes and BJTs are implanted together with the FinFET n-wells and p-wells.

Abstract: A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling.

Abstract: An electrostatic discharge (ESD) device includes a high-voltage well (HVW) region of a first conductivity type; a first heavily doped region of a second conductivity type opposite the first conductivity type over the HVW region; and a doped region of the first conductivity type contacting the first heavily doped region and the HVW region. The doped region is under the first heavily doped region and over the HVW region. The doped region has a first impurity concentration higher than a second impurity concentration of the HVW region and lower than a third impurity concentration of the first heavily doped region. The ESD device further includes a second heavily doped region of the second conductivity type over the HVW region; and a third heavily doped region of the first conductivity type over and contacting the HVW region.

Abstract: The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region.

Abstract: According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.