Abstract: A monolithic compound semiconductor structure is disclosed. The monolithic compound semiconductor structure comprises a substrate, an n-type FET epitaxial structure, an n-type etching-stop layer, a p-type insertion layer, and an npn HBT epitaxial structure, and it can be used to form an FET, an HBT, or a thyristor.

Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.

Abstract: Electrostatic discharge (ESD) protection is provided for discharging current between input and output nodes. In accordance with various embodiments, an ESD protection device includes an open-base transistor having an emitter connected to the input node and a collector connected to pass current to the output node via a resistor in response to a voltage at the input node exceeding a threshold that causes the transistor to break down. The resistor is coupled across emitter and collector regions of a second open-base transistor that is configured to turn on for passing current in response to the current across the resistor exceeding a threshold that applies a threshold breakdown voltage across the second transistor. In some implementations, an emitter and/or base of the second transistor are connected to, or are respectively the same region as, a base and a collector of the first transistor.

Abstract: A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.

Abstract: The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.

Abstract: Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.

Abstract: A semiconductor device includes at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type, a first well region of a second conductivity type, a second well region of a first conductivity type, a drift region of a second conductivity type, a collector region of a first conductivity type, and a collector contact. Each cell is disposed within the first well region, and the first well region is disposed within the second well region. The device further includes a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region, and at least one embedded region embedded in the first well region. The device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well region and the second well region.

Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

Abstract: The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.

Abstract: A semiconductor may contain a plurality of circuits each comprising at least one thyristor having a base region. The base region of at least one of the thyristors has a different doping profile than the others. When a bias circuit is used to bias the thyristors, the effect of biasing on the thyristors is found to be affected by the doping profile. In a specific embodiment, the doping concentration is higher near an electrode of the thyristor than near a supporting substrate. The different doping profiles can be achieved by using different ion implant energies.

Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.