Abstract: A device having a first terminal region and a second terminal region. The first terminal region includes fine-tune (FT) metal stripes that are separated from each other by a first distance along the longitudinal direction. The second terminal region is spaced apart from the first terminal region by at least an inter-terminal distance. The second terminal region includes coarse-tune (CT) metal stripes that are separated from each other by a second distance along the longitudinal direction. The second distance is greater than the first distance, and the inter-terminal distance greater than the second distance. Each of the FT metal stripes may be selected as a first access location, and each of the CT metal stripes may be selected as a second access location. A pair of selected first and second access locations access a sheet resistance defined by a distance therebetween.

Abstract: A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented.

Abstract: A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET.

Abstract: The present invention provides a device for electrostatic discharge and the method of manufacturing thereof. P-well is formed on the substrate, and a first N+ doped region, a second N+ doped region and a P+ doped region are formed in the P-well; both ends of each doped region adopt shallow trench isolation for isolation. A lightly doped source-drain region portion is formed between the first N+ doped region and the shallow trench isolation connected thereto. Under the source-drain region, a halo injection with an inverse type is formed. The reverse conduction voltage of the collector of the bipolar transistor is lowered through the introduction of special doped region and the adoption of lightly doped source-drain technology for manufacturing the source-drain region as well as the manufacturing of halo injection with inverse type under the source-drain region, thus reducing the trigger voltage of the device.

Abstract: An integrated circuit is made of a semiconductor material and comprises an input and/or terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as to be biased at the same time as the parasitic element under the effect of an electrostatic discharge, and more than the parasitic element to evacuate a discharge current as a priority.

Abstract: The electrostatic protection device comprises a semiconductor substrate of a first conductivity type, a well of a second conductivity type formed on the semiconductor substrate, a first diffusion layer of the first conductivity type formed on the second conductivity type well and connected to a signal terminal, a first well of the first conductivity type formed on the semiconductor substrate, a first diffusion layer of the second conductivity type formed on the first well and connected to a ground terminal, a second well of the first conductivity type formed on the semiconductor substrate and spaced apart from the first well and a second diffusion layer of the first conductivity type formed on the second well connected to a ground terminal.

Abstract: The present invention relates to an electrostatic discharge protection circuit of a semiconductor memory device to protect an internal circuit from static electricity. The electrostatic discharge protection circuit includes a first trigger unit which provides a first trigger voltage in response to static electricity transferred from at least one of a first and second voltage line. A second trigger unit provides a second trigger voltage by the static electricity in response to the first trigger voltage. An electrostatic discharge protection unit configures an electrostatic discharge path among the first voltage line, the second voltage line and an input/output pad in response the first and second trigger voltages. The electrostatic discharge speed of the electrostatic discharge protection unit is enhanced by the first and second trigger voltages.

Abstract: According to the invention there is provided a semiconductor device including: at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type; a first well region of a second conductivity type; a second well region of a first conductivity type; a drift region of a second conductivity type; a collector region of a first conductivity type; a collector contact; in which each cell is disposed within the first well region and the first well region is disposed within the second well region; the device further including: a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region; and at least one embedded region embedded in the first well region; in which the device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first reference potential of the protected circuitry, and at least one second type high dopant region coupled to a second reference potential of the IC. The SCR is triggered by an external on-chip trigger device, which is adapted for injecting a trigger current into at least one gate of the SCR.